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| features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 123 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? non-volatile program and data memories ? 2/4/8k byte of in-system prog rammable program memory flash (attiny261/461/861) endurance: 10,000 write/erase cycles ? 128/256/512 by tes in-system prog rammable eeprom (a ttiny261/461/861) endurance: 100,000 write/erase cycles ? 128/256/512 bytes internal sram (attiny261/461/861) ? programming lock for self-program ming flash program and eeprom data security ? peripheral features ? 8/16-bit timer/counter with prescaler ? 8/10-bit high speed timer/counter with separate prescaler 3 high frequency pwm outputs with separate output compare registers programmable dead time generator ? universal serial interface with start condition detector ? 10-bit adc 11 single ended channels 16 differential adc channel pairs 15 differential adc channel pairs with programmable gain (1x, 8x, 20x, 32x) ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? special microcontroller features ? debugwire on-chip debug system ? in-system programmable via spi port ? external and internal interrupt sources ? low power idle, adc noise reduction, and power-down modes ? enhanced power-on reset circuit ? programmable brown-out detection circuit ? internal calibrated oscillator ? i/o and packages ? 16 programmable i/o lines ? 20-pin soic, 32-pad mlf and 20-lead tssop ? operating voltage: ? 2.7 - 5.5v for attiny261/461/861 ? speed grade: ? attiny261/461/861: 0 - 8mhz at 2.7 - 5.5v, 0 - 16mhz at 4.5 - 5.5v ? operating temperature: auto motive (?40c to +125c) ? low power consumption ? active mode atd on: 1mhz, 2.7v, 25c: 300a ? power-down mode no watc hdog: 2.7v, 25c: 0.12a 8-bit microcontroller with 2/4/8k bytes in-system programmable flash attiny261 attiny461 attiny861 automotive 7753f?avr?01/11
2 7753f?avr?01/11 attiny261/attiny461/attiny861 1. pin configurations figure 1-1. pinout attiny261/461/861 note: the large center pad underneath the qf n/mlf package should be soldered to ground on the board to ensure good mechanical stability. 1 2 3 4 5 6 7 8 9 10 20 19 1 8 17 16 15 14 1 3 12 11 (mo s i/di/ s da/oc1a/pcint 8 ) pb0 (mi s o/do/oc1a/pcint9) pb1 ( s ck/u s ck/ s cl/oc1b/pcint10) pb2 (oc1b/pcint11) pb 3 vcc gnd (adc7/oc1d/clki/xtal1/pcint12) pb4 (adc 8 /oc1d/clko/xtal2/pcint1 3 ) pb5 (adc9/int0/t0/pcint14) pb6 (adc10/re s et/pcint15) pb7 pa0 (adc0/di/ s da/pcint0) pa1 (adc1/do/pcint1) pa2 (adc2/int1/u s ck/ s cl/pcint2) pa 3 (aref/pcint 3 ) agnd avcc pa4 (adc 3 /icp0/pcint4) pa5 (adc4/ain2/pcint5) pa6 (adc5/ain0/pcint6) pa7 (adc6/ain1/pcint7) s oic 1 2 3 4 5 6 7 8 24 2 3 22 21 20 19 1 8 17 3 2 3 1 3 0 29 2 8 27 26 25 9 10 11 12 1 3 14 15 16 nc (oc1b/pcint11) pb 3 nc vcc gnd nc (adc7/oc1d/clki/xtal1/pcint12) pb4 (adc 8 /oc1d/clko/xtal2/pcint1 3 ) pb5 nc pa2 (adc2/int1/u s ck/ s cl/pcint2) pa 3 (aref/pcint 3 ) agnd nc nc avcc pa4 (adc 3 /icp0/pcint4) nc (adc9/int0/t0/pcint14) pb6 (adc10/re s et/pcint15) pb7 nc (adc6/ain1/pcint7) pa7 (adc5/ain0/pcint6) pa6 (adc4/ain2/pcint5) pa5 nc pb2 ( s ck/u s ck/ s cl/oc1b/pcint10) pb1 (mi s o/do/oc1a/pcint9) pb0 (mo s i/di/ s da/oc1a/pcint 8 ) nc nc nc pa0 (adc0/di/ s da/pcint0) pa1 (adc1/do/pcint1) qfn/mlf (oc1b/pcint11)pb 3 vcc gnd qfn/mlf 1 2 3 4 5 15 14 1 3 12 11 6 7 8 9 10 20 19 1 8 17 16 agnd avcc ( s ck/u s ck/ s cl/oc1b/pcint10) pb2 (adc7/oc1d/clki/xtal1/pcint12) pb4 pb1 (mi s o/do/oc1a/pcint9) pb0 (mo s i/di/ s da/oc1a/pcint 8 ) pa0 (adc0/di/ s da/pcint0) pa1 (adc1/do/pcint1) pa2 (adc2/int1/u s ck/ s cl/pcint2) pa 3 (aref/pcint 3 ) pa4 (adc 3 /icp0/pcint4) pa5 (adc4/ain2/pcint5) (adc5/ain0/pcint6) pa6 (adc6/ain1/pcint7) pa7 (adc10/re s et/pcint15) pb7 (adc9/int0/t0/pcint14) pb6 (adc 8 /oc1d/clko/xtal2/pcint1 3 ) pb5 3 7753f?avr?01/11 attiny261/attiny461/attiny861 1.1 disclaimer typical values contained in this data sheet are based on simulations and characterization of other avr microcontrollers manufactured on the same process technology. min and max values will be available after the device is characterized. 1.2 automotive quality grade the attiny261/461/861 have been developed and manufactured according to the most stringent requirements of the international standard iso-ts 16949. this data sheet contains limit values extracted from the results of extensive characterization (temperature and voltage). the quality and reliability of the attiny261/4 61/861 have been verified during regular product qu alification as per aec-q100 grade 1. as indicated in the ordering information paragraph, the product is available in only one tempera- ture grade, table 1-1. table 1-1. temperature grade identification for automotive products temperature temperature identifier comments ?40; +125 z full automotive temperature range 4 7753f?avr?01/11 attiny261/attiny461/attiny861 2. overview the attiny261/461/861 is a low-power cmos 8-bi t microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the attiny261/461/861 achieves throughputs ap proaching 1 mips per mhz allowing the system designer to optimize power consum ption versus processing speed. 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. port a ( 8 ) port b ( 8 ) u s i timer/co u nter1 timer/co u nter0 a/d conv. intern a l b a ndg a p an a log comp. s ram fl as h eeprom w a tchdog o s cill a tor w a tchdog timer o s cill a tor circ u it s / clock gener a tion power su pervi s ion por / bod & re s et vcc gnd program logic de bu gwire agnd aref avcc data b u s pa[0..7] pb[0..7] 11 re s et xtal[1..2] cpu 3 5 7753f?avr?01/11 attiny261/attiny461/attiny861 the attiny261/461/861 provides the following feat ures: 2/4/8k byte of in-system programmable flash, 128/256/512 bytes eeprom, 128/256/512 bytes sram, 6 general purpose i/o lines, 32 general purpose working registers, one 8-bit timer/counter with compare modes, one 8-bit high speed timer/counter, universal serial interface, internal and external interrupts, a 4-channel, 10-bit adc, a programmable watc hdog timer with in ternal oscillato r, and three so ftware select- able power saving modes. the idle mode stops the cpu while allowing the sram, timer/counter, adc, analog comparator, and interrupt system to continue functioning. the power-down mode saves the register contents, di sabling all chip functions until the next inter- rupt or hardware reset. the adc noise reduction mode stops the cpu and all i/o modules except adc, to minimize switch ing noise during adc conversions. the device is manufactured using atmel ? ?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be re-programmed in-system through an spi serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the avr core. the attiny261/461/861 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emu- lators, and evaluation kits. 2.2 pin descriptions 2.2.1 vcc supply voltage. 2.2.2 gnd ground. 2.2.3 avcc analog supply voltage. 2.2.4 agnd analog ground. 2.2.5 port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the attiny261/461/861 as listed on page 66 . 6 7753f?avr?01/11 attiny261/attiny461/attiny861 2.2.6 port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the attiny261/461/861 as listed on page 63 . 2.2.7 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 23-3 on page 190 . shorter pulses are not guaranteed to generate a reset. 7 7753f?avr?01/11 attiny261/attiny461/attiny861 3. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr. 8 7753f?avr?01/11 attiny261/attiny461/attiny861 4. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. 9 7753f?avr?01/11 attiny261/attiny461/attiny861 5. avr cpu core 5.1 overview this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. figure 5-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n 10 7753f?avr?01/11 attiny261/attiny461/attiny861 the fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle ar ithmetic logic unit (alu ) operation. in a typ- ical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and uncon ditional jump and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word for- mat. most avr instructions are 16-bit wide. there are also 32-bit instructions. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the total sram size an d the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control r egisters in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector posi- tion. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functi ons as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. 5.2 alu ? arithm etic logic unit the high-performance avr alu operates in dire ct connection with all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 11 7753f?avr?01/11 attiny261/attiny461/attiny861 5.3 status register the status register contains information about the result of the most recently executed arithme- tic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specified in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. 5.3.1 sreg ? avr status register the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for th e interrupts to be enabled. the individual inter- rupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (b it store) use the t-bit as source or desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operation s. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v suppor ts two?s complement arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. bit 76543210 0x3f (0x5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 12 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set description? for de tailed information. 5.4 general purpose register file the register file is optimized for the avr enhanc ed risc instruction set. in order to achieve the required performance and flex ibility, the following in put/output schemes ar e supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 5-2 shows the structure of the 32 general purpose working registers in the cpu. figure 5-2. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 5-2 , each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being physically imple- mented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 7 0 addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 13 7753f?avr?01/11 attiny261/attiny461/attiny861 5.4.1 the x-register, y-register, and z-register the registers r26..r31 have some added functions to their general purpose usage. these reg- isters are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 5-3 on page 13 . figure 5-3. the x-, y-, and z-registers in the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.5 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer register always points to the top of the stack. note that the stack is implemented as growing from higher memory loca- tions to lower memory locations. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above 0x60. the stack pointer is decrement ed by one when data is pushed onto the stack with the push instruction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incremented by two when data is popped from the stack with return from subroutine ret or return from interrupt reti. the avr stack pointer is implemented as two 8- bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in some implementa- tions of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e) 14 7753f?avr?01/11 attiny261/attiny461/attiny861 5.5.1 sph and spl ? stack pointer register 5.6 instruction execution timing this section describes the general access timi ng concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clo ck division is used. figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the har- vard architecture and the fast access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corr esponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 5-4. the parallel instruction fetches and instruction executions figure 5-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destina- tion register. figure 5-5. single cycle alu operation bit 1514131211109 8 0x3e (0x5e) sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph 0x3d (0x5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 15 7753f?avr?01/11 attiny261/attiny461/attiny861 5.7 reset and inte rrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 50 . the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vec- tor in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt fl ag will be set and remember ed until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is clea red, the corres ponding interrupt fl ag(s) will be set and remembered until the global interrupt enable bit is set, and will then be exec uted by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the in terrupt will not be triggered. when the avr exits from an inte rrupt, it will always retu rn to the main pr ogram and execute one more instruction be fore any pending interrupt is served. note that the status register is not automatica lly stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the interrup ts will be immediately disabled. no interrupt will be executed af ter the cli instruction, even if it occurs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. 16 7753f?avr?01/11 attiny261/attiny461/attiny861 when using the sei instruction to enable interr upts, the instruction following sei will be exe- cuted before any pending interrupts, as shown in this example. 5.7.1 interrupt response time the interrupt execution response for all the enabl ed avr interrupts is four clock cycles mini- mum. after four clock cycles the program vector address for the actual interrupt handling routine is executed. during this four clock cycle period, the program counter is pushed onto the stack. the vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. if an interrupt occurs during execution of a multi- cycle instruction, this in struction is completed before the interrupt is served. if an interrupt occurs when the mcu is in sleep mode, the interrupt execution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt handling routine take s four clock cycles. during these four clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the i-bit in sreg is set. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 18 7753f?avr?01/11 attiny261/attiny461/attiny861 when using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o registers, and the 128/256/512 bytes of inter- nal data sram in the attiny261/461/861 are all accessible through all these addressing modes. the register file is described in ?general purpose register file? on page 12 . figure 6-2. data memory map 6.2.1 data memory access times this section describes the general access timi ng concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 6-3 . figure 6-3. on-chip data sram access cycles 6.3 eeprom data memory the attiny261/46 1/861 contains 128/256/51 2 bytes of data eeprom me mory. it is organized as a separate data spac e, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described in the following, specif ying the eeprom address registers, the eeprom data register, and the eeprom control register. for a detailed description of serial data downloading to the eeprom, see page 183 . 32 registers 64 i/o registers internal sram (128/256/512 x 8) 0x0000 - 0x001f 0x0020 - 0x005f 0x0df/0x15f/0x25f 0x0060 data memory clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 19 7753f?avr?01/11 attiny261/attiny461/attiny861 6.3.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access times for the eeprom are given in table 6-1 . a self-timing function, however, lets the user software detect when the next byte can be written. if the user code contains instruc- tions that write the eeprom, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on po wer-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. see ?preventing eeprom co rruption? on page 21 for details on how to avoid problems in these situations. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. refer to ?atomic byte programming? on page 19 and ?split byte programming? on page 19 for details on this. when the eeprom is read, the cpu is halted for fo ur clock cycles before the next in struction is executed. when the eeprom is written, the cp u is halted for two clock cycles before the next instruction is executed. 6.3.2 atomic byte programming using atomic byte programming is the simplest mode. when writing a by te to the eeprom, the user must write the address in to the eearl register and data into eedr register. if the eepmn bits are zero, writing eepe (within four cycles after eem pe is written) will trigger the erase/write operation. both the erase and write cycle are done in one operation and the total programming time is give n in table 1. the eepe bit remains set until th e erase and write opera- tions are completed. while the device is busy with programming, it is not possible to do any other eeprom operations. 6.3.3 split byte programming it is possible to split the erase and write cycle in two different operations. this may be useful if the system requires short access time for some limited period of ti me (typically if the power sup- ply voltage falls). in order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. but since the erase and write operations are split, it is possible to do the erase operations when the system allows doing time-critical operations (typically after power-up). 6.3.4 erase to erase a byte, the address must be written to eear. if the eepmn bits are 0b01, writing the eepe (within four cycles after eempe is written) will trigger the er ase operation on ly (program- ming time is given in table 1). the eepe bit remains set until the erase operation completes. while the device is bu sy programming, it is not possible to do any other eeprom operations. 6.3.5 write to write a location, the user must write the address into eear and the data into eedr. if the eepmn bits are 0b10, writing the eepe (within f our cycles after eempe is written) will trigger the write operation only (programming time is given in t able 1). the eepe bit remains set until the write operation completes. if the location to be written has not been erased before write, the data that is stored must be considered as lost. while the device is busy with programming, it is not possible to do any other eeprom operations. 20 7753f?avr?01/11 attiny261/attiny461/attiny861 the calibrated oscillator is used to time the eeprom accesses. make sure the oscillator fre- quency is within the requirements described in ?osccal ? oscillator ca libration register? on page 32 . the following code examples show one assembly and one c function for erase, write, or atomic write of the eeprom. the examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during ex ecution of th ese functions. assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set programming mode ldi r16, (0< 23 7753f?avr?01/11 attiny261/attiny461/attiny861 6.5.2 eedr ? eeprom data register ? bits 7:0 ? eedr7:0: eeprom data for the eeprom write operation the eedr register contains the data to be written to the eeprom in the address given by the eear regi ster. for the eeprom read operation, the eedr contains the data read out from the eeprom at the add ress given by eear. 6.5.3 eecr ? eeprom control register ? bit 7 ? res: reserved bit this bit is reserved for future use and will always read as 0 in attiny261/461/861. for compati- bility with future avr devices, always write this bit to zero. af ter reading, mask out this bit. ? bit 6 ? res: reserved bit this bit is reserved in the attiny26 1/461/861 and will always read as zero. ? bits 5, 4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bits setting defines which programming action that will be triggered when writing eepe. it is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations in two different operations. the programming times for the different modes are shown in table 6-1 . while eepe is set, any write to eepmn will be ignored. du ring reset, the eepmn bits will be reset to 0b00 unless the eeprom is busy programming. ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enab les the eeprom ready interrupt if th e i-bit in sreg is set. writing eerie to zero disables the interrupt. the eep rom ready interrupt generates a constant inter- rupt when non-volatile memory is ready for programming. bit 76543210 0x1d (0x3d) eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x1c (0x3c) ? ? eepm1 eepm0 eerie eempe eepe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 table 6-1. eeprom mode bits eepm1 eepm0 programming time operation 0 0 3.4 ms erase and write in one operation (atomic operation) 0 1 1.8 ms erase only 1 0 1.8 ms write only 1 1 ? reserved for future use 24 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bit 2 ? eempe: eeprom master program enable the eempe bit determines whether writing eepe to o ne will have effect or not. when eempe is set, setting eepe within four cl ock cycles will program the eeprom at the selected address. if eempe is zero, setting eepe will have no effect. when eempe has been written to one by software, hardware clears the bit to zero after four clock cycles. ? bit 1 ? eepe: eeprom program enable the eeprom program enable signal eepe is th e programming enable signal to the eeprom. when eepe is written, the eeprom will be pr ogrammed according to the eepmn bits setting. the eempe bit must be written to one before a logical one is written to eepe, otherwise no eeprom write takes place. when the write access time has elapsed, the eepe bi t is cleared by hardware. when eepe has been set, the cpu is ha lted for two cycles befo re the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal ? eere ? is t he read strobe to the eeprom. when the cor- rect address is set up in the eear register, the eere bit must be written to one to trigger the eeprom read. the eeprom read access takes one instruction, and th e requested data is available immediately. when t he eeprom is read, the cpu is ha lted for four cycles before the next instruction is executed. th e user should poll the eepe bit be fore starting the read opera- tion. if a write operation is in progress, it is neither possible to read the eeprom, nor to change the eear register. 6.5.4 gpior2 ? general purpose i/o register 2 6.5.5 gpior1 ? general purpose i/o register 1 6.5.6 gpior0 ? general purpose i/o register 0 bit 76543210 0x0c (0x2c) msb lsb gpior2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x0b (0x2b) msb lsb gpior1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x0a (0x2a) msb lsb gpior0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 25 7753f?avr?01/11 attiny261/attiny461/attiny861 7. system clock and clock options 7.1 clock systems and their distribution figure 7-1 presents the principal clock systems in the avr and their distribution. all of the clocks need not be active at a given time. in order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ?power manage- ment and sleep modes? on page 35 . the clock systems are detailed below. figure 7-1. clock distribution 7.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of the system concerned with operation of the avr core. examples of such modules are the general pur pose register file, the status register and the data memory holding the stack pointer. halting the cpu clock inhibits the core from performing general operations and calculations. 7.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, like timer/counter. the i/o clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is halted. 7.1.3 flash clock ? clk flash the flash clock controls operation of the flash in terface. the flash clock is usually active simul- taneously with the cpu clock. 7.1.4 adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accurate adc conversion results. 26 7753f?avr?01/11 attiny261/attiny461/attiny861 7.1.5 internal pll for fast peripheral clock generation - clk pck the internal pll in attiny261/461/861 generates a clock frequency that is 8x multiplied from a source input. by default, the pll uses the output of the internal 8.0 mhz rc oscillator as source. alternatively, if the lsm bit of the pllcsr is set the pll will use the outp ut of the rc oscillator divided by two. thus the output of the pll, the fa st peripheral clock is 64 mhz. the fast periph- eral clock, or a clock prescaled from that, can be selected as the clock source for timer/counter1or as a system clock. see figure 7-2 . the frequency of the fast peripheral clock is divided by two when lsm of pllcsr is set, resulting in a clock frequency of 32 mhz. note, that lsm can not be set if pll clk is used as a system clock. figure 7-2. pck clocking system the pll is locked on the rc oscillator and adju sting the rc oscillator via osccal register will adjust the fast peripheral clock at the same time. however, even if the rc oscillator is taken to a higher frequency than 8 mhz, the fast peripheral clock frequency saturates at 85 mhz (worst case) and remains oscillating at the maximum frequency. it should be noted that the pll in this case is not locked any longer with the rc oscillator clock. therefore, it is recommended not to take the osccal adjustments to a higher frequency than 8 mhz in order to keep the pll in the correct operating range. the internal pll is enabled when: ? the plle bit of the pllcsr register is set. ? the cksel fuse are programmed to ?0001?. the pllcsr bit plock is set when pll is locked. both internal rc oscillator and pll are switched off in power down and stand-by sleep modes. 1/2 8 mhz l s m 8 .0 mhz o s cillator pll 8 x ck s el 3 :0 plle o s ccal 4 mhz 1/4 lock detector pre s caler clkp s3 :0 s y s tem clock plock pck o s cillator s xtal1 xtal2 64 / 3 2 mhz 8 mhz 16 mhz 27 7753f?avr?01/11 attiny261/attiny461/attiny861 7.2 clock sources the device has the following clock source options, selectable by flash fuse bits as shown below. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. the various choices for each clocking option is given in the following sections. when the cpu wakes up from power-down or power-save, the selected clock source is used to time the start-up, ensuring stable oscilla tor operation before in struction execution starts. when the cpu starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. the watchdog oscillator is used for timing this real-time part of the start-up time. the number of wdt oscillator cycles used for each time-out is shown in table 7-2 . 7.3 default clock source the device is shipped with cksel = ?0010?, sut = ?10?, and ckdiv8 programmed. the default clock source setting is therefor e the internal rc oscillator running at 8 mhz with longest start-up time and an initial system clock prescaling of 8. this default setting ensures that all users can make their desired clock source setting using an in-system or high-voltage programmer. 7.4 external clock to drive the device from an external clock source, clki should be driven as shown in figure 7-3 . to run the device on an ex ternal clock, the cksel fuses must be programme d to ?0000?. table 7-1. device clocking options select (1) vs. pb4 and pb5 functionality device clocking option cksel3..0 pb4 pb5 external clock 0000 xtal1 i/o pll clock 0001 i/o i/o calibrated internal rc oscillator 8.0 mhz 0010 i/o i/o watchdog oscillator 128 khz 0011 i/o i/o external low-frequency crystal 01xx xtal1 xtal2 external crystal/ceramic resonator (0.4 - 0.9 mhz) 1000 xtal1 xtal2 external crystal/ceramic resonator (0.4 - 0.9 mhz) 1001 xtal1 xtal2 external crystal/ceramic resonator (0.9 - 3.0 mhz) 1010 xtal1 xtal2 external crystal/ceramic resonator (0.9 - 3.0 mhz) 1011 xtal1 xtal2 external crystal/ceramic resonator (3.0 - 8.0 mhz) 1100 xtal1 xtal2 external crystal/ceramic resonator (3.0 - 8.0 mhz) 1101 xtal1 xtal2 external crystal/ceramic resonator (8.0 - 16.0 mhz) 1110 xtal1 xtal2 external crystal/ceramic resonator (8.0 - 16.0 mhz) 1111 xtal1 xtal2 table 7-2. number of watchdog oscillator cycles typ time-out number of cycles 4 ms 512 64 ms 8k (8,192) 28 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 7-3. external clock drive configuration when this clock source is sele cted, start-up times are determined by the sut fuses as shown in table 7-3 . note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuri ng stable operation. refer to ?system clock prescaler? on page 32 for details. 7.5 high frequency pll clock - pll clk there is an internal pll that provides nominally 64 mhz clock rate locked to the rc oscillator for the use of the peripheral timer/counter1 and for the system clock source. when selected as a system clock source, by programming the cksel fuses to ?0001?, it is divided by four like shown in table 7-4 . when this clock source is selected, start-up times are determined by the sut fuses as shown in table 7-5 . see also ?pck clocking system? on page 26 . table 7-3. start-up times for the external clock selection sut1..0 start-up time from power-down and power-save additional delay from reset recommended usage 00 6 ck 14ck bod enabled 01 6 ck 14ck + 4 ms fast rising power 10 6 ck 14ck + 64 ms slowly rising power 11 reserved external clock signal clki gnd table 7-4. pllck operating modes cksel3..0 nominal frequency 0001 16 mhz table 7-5. start-up times for the pllck sut1..0 start-up time from power down additional delay from power-on-reset (v cc = 5.0v) recommended usage 00 14ck + 1k (1024) + 4 ms 4 ms bod enabled 01 14ck + 16k (16384) + 4 ms 4 ms fast rising power 10 14ck + 1k (1024) + 64 ms 4 ms slowly rising power 11 14ck + 16k (16384) + 64 ms 4 ms slowly rising power 29 7753f?avr?01/11 attiny261/attiny461/attiny861 7.6 calibrated internal rc oscillator by default, the internal rc os cillator provides an approximat e 8.0 mhz clock. though voltage and temperature dependent, this clock can be very accurately calibrated by the user. see table 23-1 on page 189 and ?internal oscillator speed? on page 207 for more details. the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 32 for more details. this clock may be selected as the system clock by programming the cksel fuses as shown in table 7-6 on page 29 . if selected, it will operate with no external components. during reset, hardware loads the pre-programmed calibration value into the osccal register and thereby automatically calibrates the rc oscillator. the accu racy of this calibration is shown as factory calibration in table 23-1 on page 189 . by changing the osccal register from sw, see ?osccal ? oscillator ca libration register? on page 32 , it is possible to get a higher calibration accuracy than by using the factory calibration. the accuracy of this calibration is shown as user calibration in table 23-1 on page 189 . when this oscillator is used as the chip clock, the watchdog oscillator will still be used for the watchdog timer and for the reset time-out. for more information on the pre-programmed cali- bration value, see the section ?calibration byte? on page 173 . notes: 1. the device is shipped with this option selected. 2. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. when this oscillator is select ed, start-up times are determined by the sut fuses as shown in table 7-7 on page 29 . note: 1. the device is shipped with this option selected. table 7-6. internal calibrated rc o scillator operating modes (1)(2) frequency range (mhz) cksel3..0 7.84 - 8.16 0010 table 7-7. start-up times for the internal calib rated rc oscillato r clock selection sut1..0 start-up time from power-down additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck 14ck bod enabled 01 6 ck 14ck + 4 ms fast rising power 10 (1) 6 ck 14ck + 64 ms slowly rising power 11 reserved 30 7753f?avr?01/11 attiny261/attiny461/attiny861 7.7 128 khz internal oscillator the 128 khz internal oscillator is a low power oscillator providing a clock of 128 khz. the fre- quency is nominal at 3v and 25c. this cl ock may be select as the system clock by programming the cksel fuses to ?0011?. when this clock source is sele cted, start-up times are determined by the sut fuses as shown in table 7-8 . 7.8 low-frequency crystal oscillator to use a 32.768 khz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting cksel fu ses to ?0100?. the cryst al should be connected as shown in figure 7-4 . refer to the 32 khz crystal oscilla tor application note for details on oscillator operation and how to choose appropriate values for c1 and c2. when this oscillator is selected, start-up ti mes are determined by t he sut fuses as shown in table 7-9 . notes: 1. these options should only be used if frequen cy stability at start-up is not important for the application. 7.9 crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be con- figured for use as an on-chip oscillator, as shown in figure 7-4 . either a quartz crystal or a ceramic resonator may be used. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 7-10 . for ceramic resonators, the capacitor values given by the manufacturer should be used. table 7-8. start-up times for the 128 khz internal oscillator sut1..0 start-up time from power-down and power-save additional delay from reset recommended usage 00 6 ck 14ck bod enabled 01 6 ck 14ck + 4 ms fast rising power 10 6 ck 14ck + 64 ms slowly rising power 11 reserved table 7-9. start-up times for the lo w frequency crystal oscillator clock selection sut1..0 start-up time from power down and power save additional delay from reset (v cc = 5.0v) recommended usage 00 1k (1024) ck (1) 4 ms fast rising power or bod enabled 01 1k (1024) ck (1) 64 ms slowly rising power 10 32k (32768) ck 64 ms stab le frequency at start-up 11 reserved 31 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 7-4. crystal oscillator connections the oscillator can operate in three different mo des, each optimized for a specific frequency range. the op erating mode is selected by t he fuses cksel3..1 as shown in table 7-10 . notes: 1. this option should not be used with crystals, only with ceramic resonators. the cksel0 fuse together with the sut1..0 fuses select the start-up times as shown in table 7-11 . notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start- up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with cerami c resonators and will ensure frequency stability at start-up. they can also be used with crystal s when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. table 7-10. crystal oscillator operating modes cksel3..1 frequency range (mhz) recommended range for capacitors c1 and c2 for use with crystals (pf) 100 (1) 0.4 - 0.9 ? 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 table 7-11. start-up times for the crysta l oscillator clock selection cksel0 sut1..0 start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) recommended usage 0 00 258 ck (1) 14ck + 4.1 ms ceramic resonator, fast rising power 0 01 258 ck (1) 14ck + 65 ms ceramic resonator, slowly rising power 0 10 1k (1024) ck (2) 14ck ceramic resonator, bod enabled 0 11 1k (1024)ck (2) 14ck + 4.1 ms ceramic resonator, fast rising power 1 00 1k (1024)ck (2) 14ck + 65 ms ceramic resonator, slowly rising power 1 01 16k (16384) ck 14ck crystal oscillator, bod enabled 1 10 16k (16384) ck 14ck + 4.1 ms crystal oscillator, fast rising power 1 11 16k (16384) ck 14ck + 65 ms crystal oscillator, slowly rising power xtal2 xtal1 gnd c2 c1 32 7753f?avr?01/11 attiny261/attiny461/attiny861 7.10 clock output buffer the device can output the system clock on t he clko pin. to enable the output, the ckout fuse has to be programmed. this mode is suitable when the chip clock is used to drive other cir- cuits on the system. note that the clock will not be output du ring reset and the normal operation of i/o pin will be overridden when the fuse is pr ogrammed. any clock sour ce, including the inter- nal rc oscillator, can be selected when the cl ock is output on clko. if the system clock prescaler is used, it is the divided system clock that is output. 7.11 system clock prescaler the attiny261/461/861 system clock can be divided by setting the clock prescale register ? clkpr. this feature can be used to decrease power consumption when the requirement for processing power is low. this can be used with al l clock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 7-12 . 7.11.1 switching time when switching between prescaler settings, the system clock prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the cpu?s clock frequency. hence, it is not possible to determine the state of the prescaler ? even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. from the time the clkps values ar e written, it takes between t1 + t2 and t1 + 2*t2 before the new clock frequency is active. in this interval, 2 active clock edges are produced. here, t1 is the previous clock period, and t2 is the period corresponding to the new prescaler setting. 7.12 register description 7.12.1 osccal ? oscillato r calibration register ? bits 7:0 ? cal7:0: oscillator calibration value the oscillator calibration register is used to trim the calibrated internal rc oscillator to remove process variations from the oscillator frequency. a pre-programmed calibration value is automatically written to this register during chip reset, giving the factory calibrated frequency as specified in table 23-1 on page 189 . the application software can write this register to cha nge the oscillator fre quency. the oscillator can be calibrated to frequencies as specified in table 23-1 on page 189 . calibration outside that range is not guaranteed. note that this o scillator is used to time eeprom and flash write accesses , and these write times will be affected accordingly. if the eeprom or flash are writ ten, do not calibrate to more than 8.8 mhz. other wise, the eeprom or flash write may fail. bit 76543210 0x31 (0x51) cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value 33 7753f?avr?01/11 attiny261/attiny461/attiny861 the cal7 bit determines the range of operation for the oscillator. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. the two fre- quency ranges are overlapping, in other words a setting of osccal = 0x7f gives a higher frequency than osccal = 0x80. the cal6..0 bits are used to tune the frequency within the selected range. a setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7f gives the highest frequency in the range. 7.12.2 clkpr ? clock prescale register ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enab le change of the clkps bits. the clkpce bit is only updated when the other bits in cl kpr are simultaneously wr itten to zero. clkpce is cleared by hardware four cycles af ter it is written or when the clkps bits are written. rewriting the clkpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. ? bits 6:4 ? res: reserved bits these bits are reserved bits in the atti ny261/461/861 and will alwa ys read as zero. ? bits 3:0 ? clkps3:0: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides the master clock input to the mcu, the speed of all synchronous peripher- als is reduced when a division factor is used. the division factors are given in table 7-12 . to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired valu e to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, the clkps bits will be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?0011?, giving a division factor of eight at star t up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. note that any value can be written to the clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. bit 7 6543210 0x28 (0x48) clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 34 7753f?avr?01/11 attiny261/attiny461/attiny861 table 7-12. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 35 7753f?avr?01/11 attiny261/attiny461/attiny861 8. power management and sleep modes the high performance and industry leading code efficiency makes the avr microcontrollers an ideal choice for low power applications. sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consump- tion to the application?s requirements. 8.1 sleep modes figure 7-1 on page 25 presents the different clock system s in the attiny261/461/861, and their distribution. the figure is helpful in selecting an appropriate sleep mode. table 8-1 shows the different sleep modes and their wake up sources. note: 1. for int0 and int1, only level interrupt. to enter any of the three sleep modes, the se bit in mcucr must be written to logic one and a sleep instruction must be executed. the sm1..0 bits in the mcucr register select which sleep mode (idle, adc noise r eduction, power-down, or standby) will be activated by the sleep instruct ion. see table 8-2 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the st art-up time, executes the interrupt routine, and resumes execution from the instruction followi ng sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. 8.2 idle mode when the sm1..0 bits are wri tten to 00, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing analog comparator , adc, timer/counter, watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and status register ? acsr. this will reduce power consumption in idle mode. if the adc is enabled, a conversion starts automatically when this mode is entered. table 8-1. active clock domains and wake-up sources in the different sleep modes active clock domains oscillators wake-up sources sleep mode clk cpu clk flash clk io clk adc clk pck main clock source enabled int0, int1 and pin change spm/eeprom ready adc wdt usi other i/o idle x x x x x x xxxx adc noise reduction xxx (1) x xxx power-down x (1) xx standby x (1) xx 36 7753f?avr?01/11 attiny261/attiny461/attiny861 8.3 adc noise reduction mode when the sm1..0 bits are written to 01, the sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupts, and the watchdog to continue operating (if enabled). this sleep mode halts clk i/o , clk cpu , and clk flash , while allowing the ot her clocks to run. this improves the noise environment for the ad c, enabling higher resolution measurements. if the adc is enabled, a conversion starts automatically when this mode is entered. apart form the adc conversion complete interrupt, only an external reset, a watchdog reset, a brown-out reset, an spm/eeprom ready inte rrupt, an external level interr upt on int0 or a pin change interrupt can wake up the mcu from adc noise reduction mode. 8.4 power-down mode when the sm1..0 bits are written to 10, the sleep instruction makes the mcu enter power-down mode. in this mode, the oscillator is stopped, while the external interrupts, and the watchdog continue operating (if enabled). only an external reset, a watchdog reset, a brown-out reset, an external level interrupt on int0, or a pin change interrupt can wake up the mcu. this sleep mode halts all generated clocks, allowing operation of asynchronous modules only. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to ?external interrupts? on page 52 for details . 8.5 standby mode when the sm1..0 bits are written to 11 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter st andby mode. this mode is identical to power-down with the exception t hat the oscillator is kept r unning. from sta ndby mode, the device wakes up in six clock cycles. 8.6 power reduction register the power reduction register (prr), see ?prr ? power reduction register? on page 38 , pro- vides a method to stop the clock to individual per ipherals to reduce power consumption. the current state of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled be fore stopping the clock. waking up a module, which is done by clearing the bit in prr, puts the module in the same state as before shutdown. module shutdown can be used in idle mode and ac tive mode to significantly reduce the overall power consumption. see ?supply current of i/o modules? on page 199 for examples. in all other sleep modes, the clock is already stopped. 8.7 minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possi ble of the device?s functions are operating. all functions not needed should be disabled. in particular, the following modules may need special consideration when trying to achieve th e lowest possible power consumption. 37 7753f?avr?01/11 attiny261/attiny461/attiny861 8.7.1 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be dis- abled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an extended conversion. refer to ?adc ? analog to digital converter? on page 144 for details on adc operation. 8.7.2 analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparat or should be disabled. in the other sleep modes, the analog comparator is automatically di sabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be dis- abled in all sleep modes. ot herwise, the internal volt age reference will be enabled, independent of sleep mode. refer to ?ac ? analog comparator? on page 140 for details on how to configure the analog comparator. 8.7.3 brown-out detector if the brown-out detector is not needed in the application, this module should be turned off. if the brown-out detector is enabled by the bodlevel fuses, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consumption. refer to ?brown-out detection? on page 43 for details on how to configure the brown-out detector. 8.7.4 internal voltage reference the internal voltage referenc e will be enabled when needed by the brown-out de tection, the analog comparator or the adc. if these modules are disabled as described in the sections above, the internal voltage refe rence will be disabled and it w ill not be consuming power. when turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal volt- age reference? on page 44 for details on the start-up time. 8.7.5 watchdog timer if the watchdog timer is not needed in the application, this module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper slee p modes, this will contribute signific antly to the total current consump- tion. refer to ?watchdog timer? on page 44 for details on how to configure the watchdog timer. 8.7.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important thing is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensu res that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detec ting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 59 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or has an analog signal level close to v cc /2, the input buffer will use excessive power. 38 7753f?avr?01/11 attiny261/attiny461/attiny861 for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr0, didr1). refer to ?didr0 ? digital input disable register 0? on page 163 or ?didr1 ? digital input dis- able register 1? on page 163 for details. 8.8 register description 8.8.1 mcucr ? mcu control register the mcu control register contains control bits for power management. ? bit 5 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu enteri ng the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable (se) bit to one just before the execution of the sleep instruction and to clear it immediately af ter waking up. ? bits 4, 3 ? sm1:0: sleep mode select bits 2..0 these bits select between the three available sleep modes as shown in table 8-2 . ? bit 2 ? res: reserved bit this bit is a reserved ed bit in the atti ny261/461/861 and will always read as zero. 8.8.2 prr ? power reduction register ? bits 7, 6, 5, 4- res: reserved bits these bits are reserved bits in the atti ny261/461/861 and will alwa ys read as zero. bit 76543210 0x35 (0x55) ? pud se sm1 sm0 ? isc01 isc00 mcucr read/write r r/w r/w r/w r/w r r/w r/w initial value00000000 table 8-2. sleep mode select sm1 sm0 sleep mode 00idle 0 1 adc noise reduction 1 0 power-down 1 1 standby bit 76543 2 10 0x36 (0x56) ? - - - prtim1 prtim0 prusi pradc prr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 39 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bit 3- prtim1: power reduction timer/counter1 writing a logic one to this bit shuts down the timer/counter1 module. when the timer/counter1 is enabled, operation will cont inue like before the shutdown. ? bit 2- prtim0: power reduction timer/counter0 writing a logic one to this bit shuts down the timer/counter0 module. when the timer/counter0 is enabled, operation will cont inue like before the shutdown. ? bit 1 - prusi: power reduction usi writing a logic one to this bit shuts down t he usi by stopping the clock to the module. when waking up the usi again, the usi should be re initialized to ensure proper operation. ? bit 0 - pradc: power reduction adc writing a logic one to this bit shuts down the adc. the adc must be disabled before shut down. also analog comparator needs this clock. 40 7753f?avr?01/11 attiny261/attiny461/attiny861 9. system control and reset 9.0.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. the instruction placed at the reset vector must be a rjmp ? relative jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. the circuit diagram in figure 9-1 shows the reset logic. ?system and reset character- istics? on page 190 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the dif- ferent selections for the delay period are presented in ?clock sources? on page 27 . 9.0.2 reset sources the attiny261/461/861 has four sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length. ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. ? brown-out reset. the mcu is re set when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. 41 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 9-1. reset logic 9.0.3 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in ?system and reset characteristics? on page 190 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a fa ilure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is acti vated again, without any delay, when v cc decreases below the detection level. figure 9-2. mcu start-up, reset tied to v cc mcu status register (mcusr) brown-out reset circuit bodlevel [1..0] delay counters cksel[1:0] ck timeout wdrf borf extrf porf data b u s clock generator spike filter pull-up resistor watchdog oscillator sut [ 1:0 ] power-on reset circuit reset time-out internal reset t tout v rst v pormax v cc ccrr v v pormin 42 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 9-3. mcu start-up, reset extended externally table 9-1. power on reset specifications note: 1. before rising, the supply has to be between v pormin and v pormax to ensure a reset. 9.0.4 external reset an external reset is generated by a low level on the reset pin if enabled. reset pulses longer than the minimum pulse width (see ?system and reset characteristics? on page 190 ) will gener- ate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. figure 9-4. external reset during operation symbol parameter min typ max unit v pot power-on reset threshold voltage (rising) 1.1 1.4 1.7 v power-on reset threshold voltage (falling) (1) 0.8 1.3 1.6 v v pormax vcc max. start voltage to ensure internal power-on reset signal 0.4 v v pormin vcc min. start voltage to ensure internal power-on reset signal -0.1 v v ccrr vcc rise rate to ensure power-on reset 0.01 v/ms v rst reset pin threshold voltage 0.1 v cc 0.9v cc v reset time-out internal reset t tout v rst v cc v pot cc 43 7753f?avr?01/11 attiny261/attiny461/attiny861 9.0.5 brown-out detection attiny261/461/861 has an on-chip brown-out de tection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodlevel fu ses. the trigger level has a hy steresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 9-5 ), the brown-out reset is immediately activated. when v cc increases above the trigger level (v bot+ in figure 9-5 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for lon- ger than t bod given in ?system and reset characteristics? on page 190 . figure 9-5. brown-out reset during operation 9.0.6 watchdog reset when the watchdog times out, it will generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 44 for details on operation of the watchdog timer. figure 9-6. watchdog reset during operation v cc reset time-out internal reset v bot- v bot+ t tout ck cc 44 7753f?avr?01/11 attiny261/attiny461/attiny861 9.1 internal voltage reference attiny261/461/861 features an internal bandgap re ference. this reference is used for brown-out detection, and it can be used as an input to the analog comparator or the adc. 9.1.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in ?system and reset characteristics? on page 190 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by progra mming the bodlevel [2 ..0] fuse bits). 2. when the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, after setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog comparator or adc is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. 9.2 watchdog timer the watchdog timer is clocked fr om an on-chip oscillator which runs at 128 khz. by controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted as shown in table 9-4 on page 48 . the wdr ? watchdog reset ? instruction resets the watchdog timer. the watchdog timer is also reset when it is disabled and when a chip reset occurs. ten different clock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the attiny261/461/861 resets and executes from the reset vector. for timing details on the watchdog reset, refer to table 9-4 on page 48 . the watchdog timer can also be configured to generate an interrupt instead of a reset. this can be very helpful when using the watchdog to wake-up from power-down. to prevent unintentional disabling of the watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse wdton as shown in table 9-2. refer to ?timed sequences for changing the configuration of the watchdog timer? on page 45 for details. table 9-2. wdt configuration as a function of the fuse settings of wdton wdton safety level wdt initial state how to disable the wdt how to change time-out unprogrammed 1 disabled timed sequence no limitations programmed 2 enabled always enabled timed sequence 45 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 9-7. watchdog timer 9.3 timed sequences for c hanging the configuration of the watchdog timer the sequence for changing configuration differs slightly between the two safety levels. separate procedures are described for each level. 9.3.1 safety level 1 in this mode, the watchdog time r is initially disabled, but can be enabled by writing the wde bit to one without any restriction. a timed sequence is needed when disabling an enabled watch- dog timer. to disable an enabled watchdog timer, the following procedure must be followed: 1. in the same operation, write a logic one to wdce and wde. a logic one must be written to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, in the same operation, write the wde and wdp bits as desired, but with the wdce bit cleared. 9.3.2 safety level 2 in this mode, the watchdog time r is always enabled, and the wde bit will always read as one. a timed sequence is needed when changing the watchdog time-out period. to change the watchdog time-out, the following procedure must be followed: 1. in the same operation, write a logical one to wdce and wde. even though the wde always is set, the wde must be written to one to start the timed sequence. 2. within the next four clock cycles, in the same operation, write the wdp bits as desired, but with the wdce bit cleared. the value written to the wde bit is irrelevant. 9.4 register description 9.4.1 mcusr ? mcu status register the mcu status register provides information on which reset source caused an mcu reset. osc/2k osc/4k osc/8k osc/16k osc/32k osc/64k osc/128k osc/256k osc/512k osc/1024k mcu reset watchdog prescaler 128 khz oscillator watchdog reset wdp0 wdp1 wdp2 wdp3 wde bit 76543210 0x34 (0x54) ? ? ? ? wdrf borf extrf porf mcusr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 46 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bits 7:4 ? res: reserved bits these bits are reserved bits in the atti ny261/461/861 and will alwa ys read as zero. ? bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog re set occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bi t is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset only by writing a logic zero to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. 9.4.2 wdtcr ? watchdog timer control register ? bit 7 ? wdif: watchdog timeout interrupt flag this bit is set when a time-out occurs in the watchdog timer and the watchdog timer is config- ured for interrupt. wdif is cleared by hardw are when executing the corresponding interrupt handling vector. alternatively, wdif is cleared by writing a logic one to the flag. when the i-bit in sreg and wdie are set, the watchdog time-out interrupt is executed. ? bit 6 ? wdie: watchdog timeout interrupt enable when this bit is written to one, wde is cleared, and the i-bit in the status register is set, the watchdog time-out interrupt is enabled. in this mode the corresponding interrupt is executed instead of a reset if a timeout in the watchdog timer occurs. if wde is set, wdie is automatically cleared by hardware when a time-out occurs. this is useful for keeping the watchdog reset security while using the interrupt. after the wdie bit is cleared, the next time-out will generate a reset. to avoid the watchdog reset, wdie must be set after each interrupt. bit 76543210 0x21 (0x41) wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 wdtcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0000x000 47 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bit 4 ? wdce: watchdog change enable this bit must be set when the wde bit is writte n to logic zero. otherwis e, the watchdog will not be disabled. once written to one, hardware will clear this bit after four clock cycles. refer to the description of the wde bit for a watchdog disable procedure. this bit must also be set when changing the prescaler bits. see ?timed sequences for changing the configuration of the watchdog timer? on page 45. ? bit 3 ? wde: watchdog enable when the wde is written to logic one, the watchdog timer is enabled, and if the wde is written to logic zero, the watchdog timer function is di sabled. wde can only be cleared if the wdce bit has logic level one. to disable an enabled watchdog timer, the following procedure must be followed: 1. in the same operation, write a logic one to wdce and wde. a logic one must be written to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logic 0 to wde. this disables the watchdog. in safety level 2, it is not possible to disable the watchdog timer, even with the algorithm described above. see ?timed sequences for changing the configuration of the watchdog timer? on page 45. in safety level 1, wde is overridden by wdrf in mcusr. see ?mcusr ? mcu status regis- ter? on page 45 for description of wdrf. this means that wde is always set when wdrf is set. to clear wde, wdrf must be cleared before disabling the watchdog with the procedure described above. this feature ensures multiple re sets during conditions causing failure, and a safe start-up after the failure. note: if the watchdog timer is not going to be used in the application, it is important to go through a watchdog disable procedure in the initialization of the device. if the watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which in turn will lead to a new watchdog reset. to avoi d this situation, the app lication software should always clear the wdrf flag and the wde control bit in the initialization routine. ? bits 5, 2:0 ? wdp3..0: watchdog timer prescaler 3, 2, 1, and 0 the wdp3..0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding timeout periods are shown in table 9-4 on page 48 . table 9-3. watchdog timer configuration wde wdie watchdog timer state action on time-out 0 0 stopped none 0 1 running interrupt 1 0 running reset 1 1 running interrupt 48 7753f?avr?01/11 attiny261/attiny461/attiny861 notes: 1. if selecting a reserved code wdt time-out is selected to be one of the legal selections. table 9-4. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0000 2k (2048) cycles 16 ms 0001 4k (4096) cycles 32 ms 0010 8k (8192) cycles 64 ms 0011 16k (16384) cycles 0.125 s 0100 32k (32764) cycles 0.25 s 0101 64k (65536) cycles 0.5 s 0110 128k (131072) cycles 1.0 s 0111 256k (262144) cycles 2.0 s 1000 512k (524288) cycles 4.0 s 1001 1024k (1048576) cycles 8.0 s 1010 reserved (1) 1011 1100 1101 1110 1111 49 7753f?avr?01/11 attiny261/attiny461/attiny861 the following code example shows one assembly and one c function for turning off the wdt. the example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. note: 1. the example code assumes that the part specific header file is included. assembly code example (1) wdt_off: wdr ; clear wdrf in mcusr ldi r16, (0< 51 7753f?avr?01/11 attiny261/attiny461/attiny861 address labels code comments 0x0000 rjmp reset ; reset handler 0x0001 rjmp ext_int0 ; irq0 handler 0x0002 rjmp pcint ; pcint handler 0x0003 rjmp tim1_compa ; timer1 comparea handler 0x0004 rjmp tim1_compb ; timer1 compareb handler 0x0005 rjmp tim1_ovf ; timer1 overflow handler 0x0006 rjmp tim0_ovf ; timer0 overflow handler 0x0007 rjmp usi_start ; usi start handler 0x0008 rjmp usi_ovf ; usi overflow handler 0x0009 rjmp ee_rdy ; eeprom ready handler 0x000a rjmp ana_comp ; analog comparator handler 0x000b rjmp adc ; adc conversion handler 0x000c rjmp wdt ; wdt interrupt handler 0x000d rjmp ext_int1 ; irq1 handler 0x000e rjmp tim0_compa ; timer0 comparea handler 0x000f rjmp tim0_compb ; timer0 compareb handler 0x0010 rjmp tim0_capt ; timer0 capture event handler 0x0011 rjmp tim1_compd ; timer1 compared handler 0x0012 rjmp fault_protection ; timer1 fault protection 0x0013 reset: ldi r16, low(ramend) ; main program start 0x0014 ldi r17, high(ramend); tiny861 have also sph 0x0015 out spl, r16 ; set stack pointer to top of ram 0x0016 out sph, r17 ; tiny861 have also sph 0x0017 sei ; enable interrupts 0x0018 52 7753f?avr?01/11 attiny261/attiny461/attiny861 11. external interrupts the external interrupts are triggered by the int0 or int1 pin or any of the pcint15..0 pins. observe that, if enabled, the interrupts will trigger even if the int0, int1 or pcint15..0 pins are configured as outputs. this feature provides a way of generating a software interrupt. pin change interrupts pci will trigger if any enabled pcint15..0 pin toggles. the pcmsk register control which pins contribute to the pin change interrupts. pin change interrupts on pcint15..0 are detected asynchronously. this implies that these interrupts can be used for waking the part also from sleep modes other than idle mode. the int0 and int1 interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the specification for the mcu control register ? mcucr. when the int0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. note that recogn ition of falling or rising edge inte rrupts on int0 or int1 requires the presence of an i/o clock, described in ?clock systems and their distribution? on page 25 . low level interrupt on int0 is detected asynchronously. this implies that this interrupt can be used for waking the part also from sleep modes other than idle mode. the i/o clock is halted in all sleep modes except idle mode. note that if a level triggered interrupt is used for wake-up from power-down, the required level must be held long enough for the mcu to complete the wake-up to trigger the level interrupt. if the level disappears before the end of the start-up ti me, the mcu will still wake up, but no inter- rupt will be generated. the start- up time is defined by the su t and cksel fuses as described in ?system clock and clock options? on page 25 . 11.1 register description 11.1.1 mcucr ? mcu control register the mcu register contains control bits for interrupt sense control. ? bits 1, 0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the extern al pin int0 or int1 if the sreg i-flag and the corresponding interrupt mask are set. the level and edges on the external int0 or int1 pin that activate the interrupt are defined in table 11-1 . the value on the int0 or int1 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an inter- rupt. if low level interrupt is se lected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. bit 76543210 0x35 (0x55) ? pud se sm1 sm0 ? isc01 isc00 mcucr read/writer r/wr/wr/wr/wr r/wr/w initial value00000000 table 11-1. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 or int1 generates an interrupt request. 0 1 any logical change on int0 or int1 generates an interrupt request. 1 0 the falling edge of int0 or int1 generates an interrupt request. 1 1 the rising edge of int0 or int1 generates an interrupt request. 53 7753f?avr?01/11 attiny261/attiny461/attiny861 11.1.2 gimsk ? general interrupt mask register ? bit 7 ? int1: external interrupt request 1 enable when the int1 bit is set (one) and the i-bit in the status register (sreg) is set (one), the exter- nal pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu control register (mcucr) define whether the external interrupt is activated on rising and/or fall- ing edge of the int1 pin or level sensed. activi ty on the pin will cause an interrupt request even if int1 is configured as an output. the corresponding interrupt of external interrupt request 1 is executed from the int1 interrupt vector. ? bit 6 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the exter- nal pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu control register (mcucr) define whether the external interrupt is activated on rising and/or fall- ing edge of the int0 pin or level sensed. activi ty on the pin will cause an interrupt request even if int0 is configured as an output. the corresponding interrupt of external interrupt request 0 is executed from the int0 interrupt vector. ? bit 5 ? pcie1: pin change interrupt enable when the pcie1 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt is enabled. any change on any enabled pcin t7..0 or pcint15..12 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci interrupt vector. pcint7..0 and pcint15..12 pins are enabled individually by the pcmsk0 and pcmsk1 register. ? bit 4 ? pcie0: pin change interrupt enable when the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt is enabled. an y change on any enabled pcint11..8 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci interrupt vector. pcint11..8 pins are enabled individually by the pcmsk1 register. ? bits 3..0 ? res: reserved bits these bits are reserved bits in the atti ny261/461/861 and will alwa ys read as zero. 11.1.3 gifr ? general interrupt flag register ? bit 7? intf1: external interrupt flag 1 when an edge or logic change on the int1 pin triggers an interrupt request, intf1 becomes set (one). if the i-bit in sreg and the int1 bit in gimsk are set (o ne), the mcu will jump to the cor- responding interrupt vector. the flag is cleared when the interrupt routine is executed. bit 76543210 0x3b (0x5b) int1 int0 pcie1 pcie0 ? ? ? ? gimsk read/write r/w r/w r/w r/w r r r r initial value00000000 bit 76543210 0x3a (0x5a) int1intf0pcif?????gifr read/writer/wr/wr/wrrrrr initial value00000000 54 7753f?avr?01/11 attiny261/attiny461/attiny861 alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int1 is configured as a level interrupt. ? bit 6 ? intf0: external interrupt flag 0 when an edge or logic change on the int0 pin triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in gimsk are set (o ne), the mcu will jump to the cor- responding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int0 is configured as a level interrupt. ? bit 5 ? pcif: pin change interrupt flag when a logic change on any pcint15 pin triggers an interrupt request, pcif becomes set (one). if the i-bit in sreg and the pcie bit in gimsk are set (one), the mcu will jump to the cor- responding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. ? bits 4:0 ? res: reserved bits these bits are reserved bits in the atti ny261/461/861 and will alwa ys read as zero. 11.1.4 pcmsk0 ? pin change mask register a ? bits 7:0 ? pcint7:0: pin change enable mask 7..0 each pcint7:0 bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint7:0 is set and the pcie1 bit in gimsk is set, pin change interrupt is enabled on the cor- responding i/o pin. if pcint7..0 is cleared, pin change interrupt on the corresponding i/o pin is disabled. 11.1.5 pcmsk1 ? pin change mask register b ? bits 7:0 ? pcint15:8: pin change enable mask 15..8 each pcint15:8 bit selects whether pin cha nge interrupt is enabled on the corresponding i/o pin. if pcint11:8 is set and the pcie0 bit in gimsk is set, pin change interrupt is enabled on the corresponding i/o pin, and if pcint15:12 is set and the pcie1 bit in gimsk is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint15:8 is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 0x23 (0x43) pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/writer/wr/wr/wr/w r/wr/wr/wr/w initial value11001000 bit 76543210 0x22 (0x42) pcint15 pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 pcmsk1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 55 7753f?avr?01/11 attiny261/attiny461/attiny861 12. i/o ports 12.1 overview all avr ports have true read-modi fy-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when chang- ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). each output buffer has symmetrical drive characteristics with both high sink and source capability. the pin driver is stro ng enough to drive led displays directly. all port pins have indi- vidually selectable pull-up resistors with a suppl y-voltage invariant resistance. all i/o pins have protection diodes to both v cc and ground as indicated in figure 12-1 . refer to ?electrical char- acteristics? on page 187 for a complete list of parameters. figure 12-1. i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? repre- sents the numbering letter for the port, and a lower case ?n? represents the bit number. however, when using the register or bit defines in a progr am, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o regis- ters and bit locations are listed in ?register description? on page 69 . three i/o memory address locations are allocated for each port, one each for the data register ? portx, data direction register ? ddrx, and the port input pins ? pinx. the port input pins i/o location is read only, while the data register and the data direction register are read/write. however, writing a logic one to a bit in the pinx register, will result in a toggle in the correspond- ing bit in the data register. in addition, the pu ll-up disable ? pud bit in mcucr disables the pull-up function for all pins in all ports when set. using the i/o port as general digital i/o is described in ?ports as general digital i/o? on page 56 . most port pins are multiplexed with alternate functions for the peripheral features on the device. how each alternate function interferes with the port pin is described in ?alternate port functions? on page 60 . refer to the individual module sectio ns for a full description of the alter- nate functions. c pin logic r pu see figure "general digital i/o" for details pxn 56 7753f?avr?01/11 attiny261/attiny461/attiny861 note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. 12.2 ports as gener al digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 12-2 shows a func- tional description of one i/o-port pin, here generically called pxn. figure 12-2. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are co mmon to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 12.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description? on page 69 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direct ion of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is c onfigured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data bus sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 57 7753f?avr?01/11 attiny261/attiny461/attiny861 if portxn is written logic one when the pin is conf igured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 12.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 12.2.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. norma lly, the pull-up enabled state is fully accept- able, as a high-impedent enviro nment will not notice the differenc e between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable all pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b10) as an intermediate step. table 12-1 summarizes the control signals for the pin value. 12.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 12-2 , the pinxn register bit and the preceding latch con- stitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 12-3 shows a timing dia- gram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 12-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 58 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 12-3. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system cl ock. the latch is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indi- cated by the two arrows tpd, max and tpd, min, a single signal transition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in figure 12-4 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchronizer is one system clock period. figure 12-4. synchronization when reading a software assigned pin value the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. the resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 59 7753f?avr?01/11 attiny261/attiny461/attiny861 note: 1. for the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4, until the dire ction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 12.2.5 digital input enable and sleep modes as shown in figure 12-2 , the digital input signal can be clamped to ground at the input of the schmitt-trigger. the signal denot ed sleep in the figure, is set by the mcu sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as ex ternal interrupt pins. if the external interrupt request is not e nabled, sleep is active also for these pins. sl eep is also overri dden by various other alternate functions as described in ?alternate port functions? on page 60 . if a logic high level (?one?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 61 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 12-5. alternate port functions (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are co mmon to all pins within the same port. clk i/o , sleep, and pud are common to all ports. all other signals are unique for each pin. clk rpx rrx wrx rdx wdx pud s ynchronizer wdx: write ddrx wrx: write portx rrx: read portx regi s ter rpx: read portx pin pud: pullup di s able clk i/o : i/o clock rdx: read ddrx d l q q s et clr 0 1 0 1 0 1 dixn aioxn dieoexn pvovxn pvoexn ddovxn ddoexn puoexn puovxn puoexn: pxn pull-up override enable puovxn: pxn pull-up override value ddoexn: pxn data direction override enable ddovxn: pxn data direction override value pvoexn: pxn port value override enable pvovxn: pxn port value override value dixn: digital input pin n on portx aioxn: analog input/output pin n on portx re s et re s et q q d clr q q d clr q q d clr pinxn portxn ddxn data b u s 0 1 dieovxn s leep dieoexn: pxn digital input-enable override enable dieovxn: pxn digital input-enable override value s leep: s leep control pxn i/o 0 1 ptoexn ptoexn: pxn, port toggle override enable wpx: write pinx wpx 62 7753f?avr?01/11 attiny261/attiny461/attiny861 table 12-2 summarizes the function of the overriding signals. the pin and port indexes from fig- ure 12-5 are not shown in the succeeding tables. the overriding signals are generated internally in the modules having the alternate function. the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description for further details. table 12-2. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardle ss of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital in put enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital in put is enabled/disabled when dieov is set/cleared, regardl ess of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt-trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi-directionally. 63 7753f?avr?01/11 attiny261/attiny461/attiny861 12.3.1 alternate functions of port b the port b pins with alternate function are shown in table 12-3 . the alternate pin configuration is as follows: ? port b, bit 7 - reset / dw/ adc10/ pcint15 reset, reset pin: when the rstdisbl fuse is programmed, this pin functions as a normal i/o pin, and the part will have to re ly on power-on reset and brown- out reset as its reset sources. when the rstdisbl fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an i/o pin. if pb7 is used as a reset pin, ddb 7, portb7 and pinb7 will all read 0. dw: when the debugwire enable (dwen) fuse is programmed and lock bits are unpro- grammed, the reset port pin is configured as a wire- and (open-drain) bi-directional i/o pin with pull-up enabled and becomes the communication gateway between target and emulator. adc10: adc input channel 10. note that adc input channel 10 uses analog power. pcint15: pin change interrupt source 15. ? port b, bit 6 - adc9/ t0/ int0/ pcint14 adc9: adc input channel 9. note that adc input channel 9 uses analog power. t0: timer/counter0 counter source. int0: the pb6 pin can serve as an external interrupt source 0. pcint14: pin change interrupt source 14. ? port b, bit 5 - xtal2/ clko/ adc8/ pcint13 xtal2: chip clock oscillator pin 2. used as clock pin for crystal oscillator or low-frequency crystal oscillator. when used as a clock pi n, the pin can not be used as an i/o pin. clko: the divided system clock can be output on the pb5 pin, if the ckout fuse is pro- grammed, regardless of the portb5 and ddb5 settings. it will also be output during reset. oc1d output compare match output: the pb5 pin can serve as an external output for the timer/counter1 compare match d when configured as an output (dda1 set). the oc1d pin is also the output pin for the pwm mode timer function. table 12-3. port b pins alternate functions port pin alternate function pb7 reset / dw / adc10 / pcint15 pb6 adc9 / t0 / int0 / pcint14 pb5 xtal2 / clko / oc1d / adc8 / pcint13 pb4 xtal1 / clki / oc1d / adc7 / pcint12 pb3 oc1b / pcint11 pb2 sck / usck / scl / oc1b /pcint10 pb1 miso / do / oc1a / pcint9 pb0 mosi / di / sda / oc1a / pcint8 64 7753f?avr?01/11 attiny261/attiny461/attiny861 adc8: adc input channel 8. note that adc input channel 8 uses analog power. pcint13: pin change interrupt source 13. ? port b, bit 4 - xtal1/ clki/ oc1b/ adc7/ pcint12 xtal1/clki: chip clock oscillator pin 1. used fo r all chip clock sources except internal cali- brated rc oscillator. when used as a clock pin, the pin ca n not be used as an i/o pin. oc1d : inverted output compare match output: the pb4 pin can serve as an external output for the timer/counter1 compare match d when configured as an output (dda0 set). the oc1d pin is also the inverted output pin for the pwm mode timer function. adc7: adc input channel 7. note that adc input channel 7 uses analog power. pcint12: pin change interrupt source 12. ? port b, bit 3 - oc1b/ pcint11 oc1b, output compare match output: the pb3 pin can serve as an external output for the timer/counter1 compare match b. the pb3 pin has to be configured as an output (ddb3 set (one)) to serve this function. the oc1b pin is also the output pin for the pwm mode timer function. pcint11: pin change interrupt source 11. ? port b, bit 2 - sck/ usck/ scl/ oc1b / pcint10 sck: master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input r egardless of the setting of ddb2. when the spi is enabled as a master, the data direction of this pi n is controlled by ddb2. when the pin is forced by the spi to be an input, the pull-up can still be controlled by the portb2 bit. usck: three-wire mode univer sal serial interface clock. scl: two-wire mode serial clock for usi two-wire mode. oc1b : inverted output compare match output: the pb2 pin can serve as an external output for the timer/counter1 compare match b when configured as an output (ddb2 set). the oc1b pin is also the inverted output pin for the pwm mode timer function. pcint10: pin change interrupt source 10. ? port b, bit 1 - miso/ do/ oc1a/ pcint9 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input r egardless of the setting of ddb1. when the spi is enabled as a slave, the data direction of this pi n is controlled by ddb1. when the pin is forced by the spi to be an input, the pull-up can still be controlled by the portb1 bit. do: three-wire mode universal serial interface data output. three-wire mode data output over- rides portb1 value and it is driven to the port when data direction bit ddb1 is set (one). portb1 still enables the pull-up , if the direction is inpu t and portb1 is set (one). oc1a: output compare match output: the pb1 pin can serve as an external output for the timer/counter1 compare match b when configured as an output (ddb1 set). the oc1a pin is also the output pin for the pwm mode timer function. pcint9: pin change interrupt source 9. 65 7753f?avr?01/11 attiny261/attiny461/attiny861 ? port b, bit 0 - mosi/ di/ sda/ oc1a / pcint8 mosi: spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input r egardless of the setting of ddb0. when the spi is enabled as a master, the data direction of this pi n is controlled by ddb0. when the pin is forced by the spi to be an input, the pull-up can still be controlled by the portb0 bit. di: data input in usi three-wire mode. usi three-wire mode does not override normal port functions, so pin must be configure as an input for di function. sda: two-wire mode serial interface data. oc1a : inverted output compare match output: the pb0 pin can serve as an external output for the timer/counter1 compare match b when configured as an output (ddb0 set). the oc1a pin is also the inverted output pin for the pwm mode timer function. pcint8: pin change interrupt source 8. table 12-4 and table 12-5 relate the alternate functions of port b to the overriding signals shown in figure 12-5 on page 61 . note: 1. 1 when the fuse is ?0? (programmed). table 12-4. overriding signals for alternate functions in pb7..pb4 signal name pb7/reset/dw/ adc10/pcint15 pb6/adc9/t0/int0/ pcint14 pb5/xtal2/clko/ oc1d/adc8/pcint13 (1) pb4/xtal1/oc1d / adc7/pcint12 (1) puoe rstdisbl (1) ? dwen (1) 0 intrc ? extclk intrc puov 1 0 0 0 ddoe rstdisbl (1) ? dwen (1) 0 intrc ? extclk intrc ddov debugwire transmit 0 0 0 pvoe 0 0 oc1d enable oc1d enable pvov 0 0 oc1d oc1d ptoe 0 0 0 0 dieoe 0 rstdisbl + (pcint5 ? pcie + adc9d) intrc ? extclk + pcint4 ? pcie + adc8d intrc + pcint12 ? pcie + adc7d dieov adc10d adc9d (intrc ? extclk) + adc8d intrc ? adc7d di pcint15 t0/int0/pcint14 pcint13 pcint12 aio reset / adc10 adc9 xtal2, adc8 xtal1, adc7 66 7753f?avr?01/11 attiny261/attiny461/attiny861 note: 1. intrc means that one of the internal rc oscillators are selected (by the cksel fuses), extck means that external clock is selected (by the cksel fuses). 12.3.2 alternate functions of port a the port a pins with alternate function are shown in table 12-6 . the alternate pin configuration is as follows: ? port a, bit 7- adc6/ain0/pcint7 adc6: analog to digital converter, channel 6 . ain0: analog comparator input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. pcint7: pin change interrupt source 8. table 12-5. overriding signals for alternate functions in pb3..pb0 signal name pb3/oc1b/ pcint11 pb2/sck/usck/scl/ o c1b /pcint10 pb1/miso/do/oc1a/ pcint9 pb0/mosi/di/sda/ o c1a /pcint8 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 usi_two_wire ? usipos 0 usi_two_wire ? usipos ddov 0 (usi_scl_hold + portb2 ) ? ddb2 ? usipos 0 (sda + portb0 ) ? ddb0 ? usipos pvoe oc1b enable oc1b enable + usipos ? usi_two_wire ? ddb2 oc1a enable + usipos ? usi_three_wire oc1a enable + (usi_two_wire ? ddb0 ? usipos ) pvov oc1b oc1b oc1a + (do ? usipos )oc1a ptoe 0 usitc ? usipos 00 dieoe pcint11 ? pcie pcint10 ? pcie + usisie ? usipos pcint9 ? pcie pcint8 ? pcie + (usisie ? usipos ) dieov 0 0 0 0 di pcint11 usck/scl/pcint10 pcint9 di/sda/pcint8 aio table 12-6. port b pins alternate functions port pin alternate function pa7 adc6 / ain0 / pcint7 pa6 adc5 / ain1 / pcint6 pa5 adc4 / ain2 / pcint5 pa4 adc3 /icp0/ pcint4 pa3 aref / pcint3 pa2 adc2 / int1 / usck / scl / pcint2 pa1 adc1 / do / pcint1 pa0 adc0 / di / sda / pcint0 67 7753f?avr?01/11 attiny261/attiny461/attiny861 ? port a, bit 6 - adc5/ain1/pcint6 adc5: analog to digital converter, channel 5. ain1: analog comparator input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. pcint6: pin change interrupt source 6. ? port a, bit 5 - adc4/ain2/pcint5 adc4: analog to digital converter, channel 4. ain2: analog comparator input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. pcint5: pin change interrupt source 5. ? port a, bit 4 - adc3/icp0/pcint4 adc3: analog to digital converter, channel 3. icp0: timer/counter0 input capture pin. pcint4: pin change interrupt source 4. ? port a, bit 3 - aref/pcint3 aref: external analog reference for adc. pull-up and output driver are disabled on pa3 when the pin is used as an external reference or internal voltage reference with external capacitor at the aref pin. pcint3: pin change interrupt source 3. ? port a, bit 2 - adc2/int1/usck/scl/pcint2 adc2: analog to digital converter, channel 2. int1: the pa2 pin can serve as an external interrupt source 1. usck: three-wire mode univer sal serial interface clock. scl: two-wire mode serial clock for usi two-wire mode. pcint2: pin change interrupt source 2. ? port a, bit 1 - adc1/do/pcint1 adc1: analog to digital converter, channel 1. do: three-wire mode universal serial interface data output. three-wire mode data output over- rides porta1 value and it is driven to the port when data direction bit dda1 is set. porta1 still enables the pull-up, if the direct ion is input and porta1 is set. pcint1: pin change interrupt source 1. ? port a, bit 0 - adc0/di/sda/pcint0 adc0: analog to digital converter, channel 0. 68 7753f?avr?01/11 attiny261/attiny461/attiny861 di: data input in usi three-wire mode. usi three-wire mode does not override normal port functions, so pin must be configure as an input for di function. sda: two-wire mode serial interface data. pcint0: pin change interrupt source 0. table 12-7 and table 12-8 relate the alternate functions of port a to the overriding signals shown in figure 12-5 on page 61 . table 12-7. overriding signals for alternate functions in pa7..pa4 signal name pa7/adc6/ain0/ pcint7 pa6/adc5/ain1/ pcint6 pa5/adc4/ain2/ pcint5 pa4/adc3/icp0/ pcint4 puoe0000 puov0000 ddoe0000 ddov0000 pvoe0000 pvov0000 ptoe0000 dieoe pcint7 ? pcie + adc6d pcint6 ? pcie + adc5d pcint5 ? pcie + adc4d pcint4 ? pcie + adc3d dieov adc6d adc5d adc4d adc3d di pcint7 pcint6 pcint5 icp0/pcint4 aio adc6, ain0 adc5, ain1 adc4, ain2 adc3 table 12-8. overriding signals for alternate functions in pa3..pa0 signal name pa3/aref/ pcint3 pa2/adc2/int1/ usck/scl/pcint2 pa1/adc1/do/ pcint1 pa0/adc0/di/sda/ pcint0 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 usi_two_wire ? usipos 0 usi_two_wire ? usipos ddov 0 (usi_scl_hold + portb2 ) ? ddb2 ? usipos 0 (sda + portb0 ) ? ddrb0 ? usipos pvoe 0 usi_two_wire ? ddrb2 usi_three_wire ? usipos usi_two_wire ? ddrb0 ? usipos pvov 0 0 do ? usipos 0 ptoe 0 usi_ptoe ? usipos 0 0 dieoe pcint3 ? pcie pcint2 ? pcie + int1 + adc2d + usisie ? usipos pcint1 ? pcie + adc1d pcint0 ? pcie + adc0d + usisie ? usipos dieov 0 adc2d adc1d adc0d di pcint3 usck/scl/int1/ pcint2 pcint1 di/sda/pcint0 aio aref adc2 adc1 adc0 69 7753f?avr?01/11 attiny261/attiny461/attiny861 12.4 register description 12.4.1 mcucr ? mcu control register ? bit 6 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?con- figuring the pin? on page 56 for more details about this feature. 12.4.2 porta ? port a data register 12.4.3 ddra ? port a data direction register 12.4.4 pina ? port a input pins address 12.4.5 portb ? port b data register 12.4.6 ddrb ? port b data direction register 12.4.7 pinb ? port b input pins address bit 7 6 5 4 3 2 1 0 0x35 (0x55) -pud se sm1 sm0 - isc01 isc00 mcucr read/write r r/w r/w r/w r/w r r r initial value 0 0 0 0 0 0 0 0 bit 76543210 0x1b (0x3b) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x1a (0x3a) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x19 (0x39) pina7 pina6 pina5 pina4 pi na3 pina2 pina1 pina0 pina read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x18 (0x38) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x17 (0x37) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x16 (0x36) pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a 70 7753f?avr?01/11 attiny261/attiny461/attiny861 13. timer/counter0 prescaler the timer/counter can be clocked directly by the system clock (by setting the csn2:0 = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. see table 13-1 on page 72 for details. 13.0.1 prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/counter. since the prescaler is not affected by the timer/counter?s clock select, the state of the prescaler will have implicati ons for situations w here a prescaled clock is used. one exam- ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles , where n equals the pre scaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing the timer/counter to program execution. 13.0.2 external clock source an external clock source applied to the t0 pin can be used as timer/counter clock (clk t0 ). the t0 pin is sampled once every system clock cycle by the pin synchronization logic. the synchro- nized (sampled) signal is then passed through the edge detector. figure 13-1 shows a functional equivalent block diagram of the t0 synchronizati on and edge detector logic. the registers are clocked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t 0 pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. see table 13-1 on page 72 for details. figure 13-1. t0 pin sampling the synchronization and e dge detector logic introduces a de lay of 2.5 to 3.5 system clock cycles from an edge has been applied to the t0 pin to the counter is updated. enabling and disabling of the clock input must be done when t0 has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. each half period of the external clock applie d must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the sys- tem clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (nyquist sampling theorem). tn_sync (to clock select logic) edge detector synchronization dq dq le dq tn clk i/o 71 7753f?avr?01/11 attiny261/attiny461/attiny861 however, due to variation of the system cloc k frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum fre- quency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 13-2. prescaler for timer/counter0 note: 1. the synchronization logic on the input pins ( t0) is shown in figure 13-1 . 13.1 register description 13.1.1 tccr0b ? timer/coun ter0 control register b ? bit 4 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/counter synchronization mode. in this mode, the value that is written to the psr0 bit is kept, hence keeping the prescaler reset signal asserted. this ensures that the timer/counter is halted and can be configured without the risk of advanc- ing during configuration. when the tsm bit is written to zero, the psr0 bit is cleared by hardware, and the timer/counter start counting. ? bit 3 ? psr0: prescaler reset timer/counter0 when this bit is one, the timer/counter0 prescale r will be reset. this bit is normally cleared immediately by hardware, except if the tsm bit is set. ? bits 2, 1, 0 ? cs02, cs01, cs00: clock select0, bit 2, 1, and 0 the clock select0 bits 2, 1, and 0 define the prescaling source of timer0. psr0 clear clk t0 t0 clk i/o synchronization bit 76543210 0x33 (0x53) - - - tsm psr0 cs02 cs01 cs01 tccr0b read/write r r r r/w r/w r/w r/w r/w initial value00000000 72 7753f?avr?01/11 attiny261/attiny461/attiny861 if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. table 13-1. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. 73 7753f?avr?01/11 attiny261/attiny461/attiny861 14. timer/counter0 14.1 features ? clear timer on compare match (auto reload) ? input capture unit ? four independent interrupt sources (tov0, ocf0a, ocf0b, icf0) ? 8-bit mode with two indepe ndent output compare units ? 16-bit mode with one independent output compare unit 14.2 overview timer/counter0 is a general purpose 8-/16-bit timer/counter module, with two/one output com- pare units and input capture feature. the timer/counter0 general operation is described in 8-/16-bit mode. a simplified block diagram of the 8-/16-bit timer/counter is shown in figure 14-1 . for the actual placement of i/o pins, refer to ?pinout attiny261/461/861? on page 2 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?register description? on page 85 . figure 14-1. 8-/16-bit timer/counter block diagram 14.2.1 registers the timer/counter0 low byte register (tcnt0l) and output compare registers (ocr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated to int.req. in figure 14-1 ) signals are all visible in the timer interrupt flag register (tifr). all interrupts are individually masked with the timer interrupt mask register (timsk). tifr and timsk are not shown in the figure. in 16-bit mode the timer/counter consists one more 8-bit register, the timer/counter0 high byte register (tcnt0h). furthermore, there is only one output compare unit in 16-bit mode as the two output compare registers, ocr0a and ocr0b, are combined to one 16-bit output compare register. clock select timer/counter data b u s ocrnb = tcntnl noise canceler icpn = edge detector control logic top count clear direction tovn (int. req.) ocna (int. req.) ocnb (int. req.) icfn (int. req.) tccrna tccrnb ( from analog comparator ouput ) tn edge detector ( from prescaler ) clk tn = ocrna tcntnh fixed top value 74 7753f?avr?01/11 attiny261/attiny461/attiny861 ocr0a contains the low byte of the word and ocr0b contains the high byte of the word. when accessing 16-bit registers, special procedures described in section ?accessing registers in 16-bit mode? on page 81 must be followed. 14.2.2 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output com- pare unit, in this case compare unit a or compare unit b. howe ver, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0l for accessing timer/counter0 counter value and so on. the definitions in table 14-1 are also used extensively throughout the document. 14.3 timer/counter clock sources the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t0 pin. the clock select logic is controlled by the clock select (cs02:0) bits located in the timer/counter control register 0 b (tccr0b), and controls which clock source and edge the timer/counter uses to increment its value. the timer/counter is inactive when no clock source is selected. the output from th e clock select logic is referred to as the timer clock (clk t0 ). for details on clock sources and prescaler, see ?timer/counter0 prescaler? on page 70 . 14.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 14-3 shows a block diagram of the counter and its surroundings. table 14-2. counter unit block diagram signal description (internal signals): count increment or decrement tcnt0 by 1. clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. table 14-1. definitions bottom the counter reaches the bottom when it becomes 0. max the counter reaches its maximum when it become s 0xff (decimal 255) in 8-bit mode or 0xffff (decimal 65535 ) in 16-bit mode. top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff/0xffff (max) or the value stored in the ocr0a register. data b u s tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn 75 7753f?avr?01/11 attiny261/attiny461/attiny861 the counter is incremented at each timer clock (clk t0 ) until it passes its top value and then restarts from bottom. the counting sequence is determined by the setting of the ctc0 bit located in the timer/counter control register (tccr0a). for more details about counting sequences, see ?modes of operation? on page 75 . clk t0 can be generated from an external or internal clock source, selected by the clock select bits (cs02:0). when no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the timer/counter overflow flag (tov0) is set when the counter reaches the maximum value and it can be used for generating a cpu interrupt. 14.5 modes of operation the mode of operation is defined by the timer/counter width (tcw0), input capture enable (icen0) and wave generation mode (ctc0) bits in ?tccr0a ? timer/counter0 control regis- ter a? on page 85 . table 14-3 shows the different modes of operation. 14.5.1 normal 8-bit mode in the normal 8-bit mode, see table 14-3 on page 75 , the counter (tcnt0l) is incrementing until it overruns when it passes its maximum 8-bit value (max = 0xff) and then restarts from the bottom (0x00). the overflow flag (tov0) will be set in the same timer clock cycle as the tcnt0l becomes zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal 8-bit mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. 14.5.2 clear timer on compare match (ctc) 8-bit mode in clear timer on compare or ctc mode, see table 14-3 on page 75 , the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output fre- quency. it also simplifies the operati on of counting external events. the timing diagram for the ctc mode is shown in figure 14-2 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared. table 14-3. modes of operation mode icen0 tcw0 ctc0 mode of operation top value update of ocrx at tov flag set on 0000normal 8-bit mode 0xff immediatemax (0xff) 10018-bit ctc ocr0a immediatemax (0xff) 2 0 1 x 16-bit mode 0xffff immediate max (0xffff) 3 1 0 x 8-bit input capture mode 0xff immediate max (0xff) 4 1 1 x 16-bit input capture mode 0xffff immediate max (0xffff) 76 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 14-2. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a va lue close to bottom when the counter is run- ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compar e match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. as for the normal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 14.5.3 16-bit mode in 16-bit mode, see table 14-3 on page 75 , the counter (tcnt0h/l) is a incrementing until it overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). the over flow flag (tov0) will be set in the same timer clock cycle as the tcnt0h/l becomes zero. the tov0 flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. 14.5.4 8-bit input capture mode the timer/counter0 can also be used in an 8-bit input capture mode, see table 14-3 on page 75 for bit settings. for full description, see the section ?input capture unit? on page 77 . 14.5.5 16-bit input capture mode the timer/counter0 can also be used in a 16-bit input capture mode, see table 14-3 on page 75 for bit settings. for full description, see the section ?input capture unit? on page 77 . tcntn ocnx interrupt flag set 1 4 period 2 3 77 7753f?avr?01/11 attiny261/attiny461/attiny861 14.6 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or mul- tiple events, can be applied via the icp0 pin or al ternatively, via the analog-comparator unit. the time-stamps can then be used to calculate frequenc y, duty-cycle, and other features of the sig- nal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 14-3 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. figure 14-3. input capture unit block diagram the output compare register ocr0a is a dual-purpose register that is also used as an 8-bit input capture register icr0. in 16-bit input capture mode the output compare register ocr0b serves as the high byte of the input capture register icr0. in 8-bit input capture mode the output compare register ocr0b is free to be used as a normal output compare register, but in 16-bit input capture mode the output compare unit cannot be used as there are no free output compare register(s). even though the input capture register is called icr0 in this sec- tion, it is referring to the output compare register(s). when a change of the logic level (an event) occurs on the input capture pin (icp0), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a capture will be triggered. when a c apture is triggered, the value of the counter (tcnt0) is written to the input capture register (icr0). the input capture flag (icf0) is set at the same system clock as the tcnt0 value is copied into input capture register. if enabled (ticie0=1), the input capture flag generates an input capture interrupt. the icf0 flag is auto- matically cleared when the interrupt is execut ed. alternatively the icf0 flag can be cleared by software by writing a logical one to its i/o bit location. icf0 (int.req.) analog comparator write icr0 (16-bit register) ocr0b (8-bit) noise canceler icp0 edge detector temp (8-bit) data bus (8-bit) ocr0a (8-bit) tcnt0 (16-bit counter) tcnt0h (8-bit) tcnt0l (8-bit) acic0* icnc0 ices0 aco* 78 7753f?avr?01/11 attiny261/attiny461/attiny861 14.6.1 input capture trigger source the default trigger source for the input capture unit is the input capture pin (icp0). timer/counter0 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture enable (acic0) bit in the timer/counter control register a (tccr0a). be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icp0) and the analog comparator output (aco) inputs are sampled using the same technique as for the t0 pin ( figure 13-1 on page 72 ). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. an input capture can also be triggered by software by controlling the port of the icp0 pin. 14.6.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icnc0) bit in timer/counter control register b (tccr0b). when enabled the noise canceler introduces addi- tional four system clock cycles of delay from a change applied to the input, to the update of the icr0 register. the noise canceler uses the syst em clock and is therefore not affected by the prescaler. 14.6.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in th e icr0 register before the nex t event occurs, the icr0 will be overwritten with a new value. in this case the result of the ca pture will be incorrect. when using the input capture interrupt, the icr0 register should be read as early in the inter- rupt handler routine as possible. the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icr0 register has been read. after a change of the edge, the input capture flag (icf0) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the trigger edge change is not required (if an interrupt handler is used). 14.7 output compare unit the comparator continuously compares timer/counter (tcnt0) with the output compare reg- isters (ocr0a and ocr0b), and whenever the timer/counter equals to the output compare registers, the comp arator signals a match. a match will set the output compare flag at the next timer clock cycle. in 8-bit mode the match can set either the output compare flag ocf0a or ocf0b, but in 16-bit mode the match can set only the output compare flag ocf0a as there is only one output compare unit. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. 79 7753f?avr?01/11 attiny261/attiny461/attiny861 alternatively, the flag can be cleared by software by writing a logical one to its i/o bit location. figure 14-4 shows a block diagram of the output compare unit. figure 14-4. output compare unit, block diagram 14.7.1 compare match bloc king by tcnt0 write all cpu write operations to the tcnt0h/l regi ster will block any compar e match that occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0a/b to be initialized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 14.7.2 using the output compare unit since writing tcnt0h/l will block all compare matc hes for one timer clock cycle, there are risks involved when changing tcnt0h/l when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt0h/l equals the ocr0a/b value, the compare match will be missed. 14.8 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 14-5 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value. figure 14-5. timer/counter timing diagram, no prescaling figure 14-6 shows the same timing data, but with the prescaler enabled. ocfn x (int.req.) = (8/16-bit comparator ) ocrnx data b u s tcntn clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 80 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 14-6. timer/counter timing dia gram, with prescaler (f clk_i/o /8) figure 14-7 shows the setting of ocf0a and ocf0b in normal mode. figure 14-7. timer/counter timing diagram, setting of ocf0x, with prescaler (f clk_i/o /8) shows the setting of ocf0a and the clearing of tcnt0 in ctc mode. figure 14-8. timer/counter timing diagram, ctc mode, with prescaler (f clk_i/o /8) tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk pck clk tn (clk pck /8) 81 7753f?avr?01/11 attiny261/attiny461/attiny861 14.9 accessing register s in 16-bit mode in 16-bit mode (the tcw0 bit is set to one) the tcnt0h/l and ocr0a/b or tcnt0l/h and ocr0b/a are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. the 16-bit timer/counter has a single 8-bit register for te mporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both cop- ied into the 16-bit register in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. there is one exception in the temporary register usage. in the output compare mode the 16-bit output compare register ocr0a/b is read without the temporary register, because the output compare register contains a fixed value t hat is only changed by cpu access. however, in 16-bit input capture mode the icr0 register formed by the ocr0a and ocr0b registers must be accessed with the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. 82 7753f?avr?01/11 attiny261/attiny461/attiny861 the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocr0a/b registers. note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt0h/l value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. assembly code example ... ; set tcnt0 to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt 0 h,r17 out tcnt 0 l,r16 ; read tcnt 0 into r17:r16 in r16,tcnt 0 l in r17,tcnt 0 h ... c code example unsigned int i; ... /* set tcnt0 to 0x01ff */ tcnt0h = 0x01; tcnt0l = 0xff; /* read tcnt0 into i */ i = tcnt0l; i |= ((unsigned int)tcnt0h << 8); ... 83 7753f?avr?01/11 attiny261/attiny461/attiny861 the following code examples sh ow how to do an atomic read of the tcnt0 register contents. reading any of the ocr0 register can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt0h/l value in the r17:r16 register pair. assembly code example tim0_readtcnt 0 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt 0 into r17:r16 in r16,tcnt 0 l in r17,tcnt 0 h ; restore global interrupt flag out sreg,r18 ret c code example unsigned int tim0_readtcnt0( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt0 into i */ i = tcnt0l; i |= ((unsigned int)tcnt0h << 8); /* restore global interrupt flag */ sreg = sreg; return i; } 84 7753f?avr?01/11 attiny261/attiny461/attiny861 the following code examples show how to do an atomic write of the tcnt0h/l register con- tents. writing any of the ocr0a/b registers can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to tcnt0h/l. 14.9.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. assembly code example tim0_writetcnt 0 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt 0 to r17:r16 out tcnt 0 h,r17 out tcnt 0 l,r16 ; restore global interrupt flag out sreg,r18 ret c code example void tim0_writetcnt0( unsigned int i ) { unsigned char sreg; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt0 to i */ tcnt0h = (i >> 8); tcnt0l = ( unsigned char )i; /* restore global interrupt flag */ sreg = sreg; } 85 7753f?avr?01/11 attiny261/attiny461/attiny861 14.10 register description 14.10.1 tccr0a ? timer/counter0 control register a ? bit 7? tcw0: timer/counter0 width when this bit is written to one 16- bit mode is selected as described figure 14-5 on page 79 . timer/counter0 width is set to 16-bits and the output compare registers ocr0a and ocr0b are combined to form one 16-bit output com pare register. because the 16-bit registers tcnt0h/l and ocr0b/a are accessed by the av r cpu via the 8-bit data bus, special proce- dures must be followed. these procedures are described in section ?accessing registers in 16-bit mode? on page 81 . ? bit 6? icen0: input capture mode enable when this bit is written to one, the input capture mode is enabled. ? bit 5 ? icnc0: input capture noise canceler setting this bit activates the input capture nois e canceler. when the noise canceler is acti- vated, the input from the input capture pin (icp0) is filtered. the filter function requires four successive equal valued samples of the icp0 pin for changing its output. the input capture is therefore delayed by four system clock cycles when the noise canceler is enabled. ? bit 4 ? ices0: input capture edge select this bit selects which edge on the input capture pin (icp0) that is used to trigger a capture event. when the ices0 bit is written to zero, a falling (negative) edge is used as trigger, and when the ices0 bit is written to one, a rising (positive) edge will trigger the capture. when a cap- ture is triggered according to the ices0 setting, the counter value is copied into the input capture register. the event will al so set the input capt ure flag (icf0), and this can be used to cause an input capture interrupt, if this interrupt is enabled. ? bit 3 - acic0: analog comparator input capture enable when written logic one, this bit enables the input capture function in timer/counter0 to be trig- gered by the analog comparator. the comparator output is in this case directly connected to the input capture front-end logic, making the compar ator utilize the noise canceler and edge select features of the timer/counter0 input capture interrupt. when written logic zero, no connection between the analog comparator and the input capture function exists. to make the comparator trigger the timer/counter0 input capture interrupt, the ticie0 bit in the timer interrupt mask register (timsk) must be set. ? bits 2:1 ? res: reserved bits these bits are reserved bits in the atti ny261/461/861 and will alwa ys read as zero. ? bit 0 ? ctc0: waveform generation mode this bit controls the counting sequence of the counter, the source for maximum (top) counter value, see figure 14-5 on page 79 . bit 76543210 0x15 (0x35) tcw0 icen0 icnc0 ices0 acic0 ? ? ctc0 tccr0a read/write r/w r/w r/w r/w r/w r r r/w initial value00000000 86 7753f?avr?01/11 attiny261/attiny461/attiny861 modes of operation supported by the timer/counte r unit are: normal mode (counter) and clear timer on compare match (ctc) mode (see ?modes of operation? on page 75 ). 14.10.2 tcnt0l ? timer/counter0 register low byte the timer/counter0 register low byte, tcnt0l, gives direct access, both for read and write operations, to the timer/ counter unit 8-bit counter. writing to the tcnt0l register blocks (dis- ables) the compare match on the following time r clock. modifying th e counter (tcnt0l) while the counter is running, introduces a risk of missing a compare match between tcnt0l and the ocr0x registers. in 16-bit mode the tcnt0l register contains the lower part of the 16-bit timer/counter0 register. 14.10.3 tcnt0h ? timer/count er0 register high byte when 16-bit mode is selected (the tcw0 bit is set to one) the timer/counter register tcnt0h combined to the timer/counter register tcnt0l gives direct access, both for read and write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is per- formed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing registers in 16-bit mode? on page 81 14.10.4 ocr0a ? timer/counter0 output compare register a the output compare register a contains an 8-bi t value that is continuously compared with the counter value (tcnt0l). a match can be used to generate an output compare interrupt. in 16-bit mode the ocr0a register contains the low byte of the 16-bit output compare register. to ensure that both the high and the low bytes are written simultaneously when the cpu writes to these registers, the access is performed usi ng an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing registers in 16-bit mode? on page 81 . 14.10.5 ocr0b ? timer/counter0 output compare register b the output compare register b contains an 8-bi t value that is continuously compared with the counter value (tcnt0l in 8-bit mode and tcnth in 16-bit mode). a match can be used to gen- erate an output compare interrupt. bit 76543210 0x32 (0x52) tcnt0l[7:0] tcnt0l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x14 (0x34) tcnt0h[7:0] tcnt0h read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x13 (0x33) ocr0a[7:0] ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x12 (0x32) ocr0b[7:0] ocr0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 87 7753f?avr?01/11 attiny261/attiny461/attiny861 in 16-bit mode the ocr0b register contains the high byte of the 16-bit output compare regis- ter. to ensure that both the high and the low bytes are written simultaneously when the cpu writes to these registers, the access is perf ormed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing reg- isters in 16-bit mode? on page 81 . 14.10.6 timsk ? timer/counter0 interrupt mask register ? bit 4 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is written to one, and th e i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 3 ? ocie0b: timer/counter output compare match b interrupt enable when the ocie0b bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enab led. the corresponding interrupt is executed if a compare match in timer/counter occurs, i.e., when the ocf0b bit is set in the timer/counter interrupt flag register ? tifr0. ? bit 1 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, and the i-bit in the status register is set, the timer/counter0 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter 0 inter- rupt flag register ? tifr0. ? bit 0 ? ticie0: timer/counter0, input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 input capture interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 50. ) is executed when the icf0 flag, located in tifr, is set. bit 76543210 0x39 (0x59) ocie1d ocie1a ocie1b ocie0a ocie0b toie1 toie0 ticie0 timsk read/write r/w r/w r/w r/w r/w r/w r/w r initial value00000000 88 7753f?avr?01/11 attiny261/attiny461/attiny861 14.10.7 tifr ? timer/counter0 interrupt flag register ? bit 4? ocf0a: output compare flag 0 a the ocf0a bit is set when a compare match occurs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the cor- responding interrupt handling vector. alternativel y, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match interrupt is executed. the ocf0a is also set in 16-bit mode when a compare match occurs between the timer/coun- ter and 16-bit data in ocr0b/a. the ocf0a is not set in input capture mode when the output compare register ocr0a is used as an input capture register. ? bit 3 ? ocf0b: output compare flag 0 b the ocf0b bit is set when a compare match occurs between the timer/counter and the data in ocr0b ? output compare register0 b. ocf0b is cleared by hardware when executing the cor- responding interrupt handling vector. alternatively, ocf0b is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0b (timer/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. the ocf0b is not set in 16-bit output compare mode when the output compare register ocr0b is used as the high byte of the 16-bit output compare register or in 16-bit input cap- ture mode when the output compare register ocr0b is used as the hi gh byte of the input capture register. ? bit 1 ? tov0: timer/counter0 overflow flag the bit tov0 is set when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i-bit, toie0 (timer/counter0 overflow interrupt enable), and tov0 are set, the timer/counter0 overflow interrupt is executed. ? bits 0 ? icf0: timer/counter0, input capture flag this flag is set when a capture event occurs on the icp0 pin. when the input capture register (icr0) is set to be used as the top value, the icf0 flag is set when the counter reaches the top value. icf0 is automatically cleared when the input capt ure interrupt vector is executed. alternatively, icf0 can be cleared by writing a logic one to its bit location. bit 76543210 0x38 (0x58) ocf1d ocf1a ocf1b ocf0a ocf0b tov1 tov0 icf0 tifr read/write r/w r/w r/w r/w r/w r/w r/w r initial value00000000 89 7753f?avr?01/11 attiny261/attiny461/attiny861 15. timer/counter1 prescaler figure 15-1 shows the timer/counter1 prescaler that supports two clocking modes, a synchro- nous clocking mode and an asynchronous clo cking mode. the synchronous clocking mode uses the system clock (ck) as a clock timebase and asynchronous mode uses the fast peripheral clock (pck) as a clock time base. the pcke bi t from the pllcsr register enables the asyn- chronous mode when it is set (?1?). figure 15-1. timer/counter1 prescaler in the asynchronous clocking mode the clock se lections are from pck to pck/16384 and stop, and in the synchronous clocking mode the clock selections are from ck to ck/16384 and stop. the clock options are described in table 15-1 on page 91 and the timer/counter1 control reg- ister, tccr1b. the frequency of the fast peripheral clock is 64 mhz or 32 mhz in low speed mode (the lsm bit in pllcsr register is set to one). the low speed mode is recommended to use when the sup- ply voltage below 2.7 volts are used. 15.0.1 prescaler reset setting the psr1 bit in tccr1b register resets the prescaler. it is possible to use the prescaler reset for synchronizing the timer/counter to program execution. 15.0.2 prescaler initialization for asynchronous mode to change timer/counter1 to the asynchronous mode follow the procedure below: 1. enable pll. 2. wait 100 s for pll to stabilize. 3. poll the plock bit until it is set. 4. set the pcke bit in the pllcsr regist er which enables the asynchronous mode. timer/counter1 count enable psr1 cs10 cs11 cs12 pck 64/32 mhz 0 cs13 14-bit t/c prescaler t1ck/2 t1ck t1ck/4 t1ck/8 t1ck/16 t1ck/32 t1ck/64 t1ck/128 t1ck/256 t1ck/512 t1ck/1024 t1ck/2048 t1ck/4096 t1ck/8192 t1ck/16384 s a ck pcke t1ck 90 7753f?avr?01/11 attiny261/attiny461/attiny861 15.1 register description 15.1.1 pllcsr ? pll control and status register ? bit 7- lsm: low speed mode the low speed mode is set, if the lsm bit is written to one. then the fast peripheral clock is scaled down to 32 mhz. the low speed mode must be set, if the supply voltage is below 2.7 volts, because the timer/counter1 is not running fast enough on low voltage levels. it is recom- mended that the timer/counter1 is sto pped whenever the lsm bit is changed. note, that lsm can not be set if pll clk is used as a system clock. ? bit 6:3- res: reserved bits these bits are reserved bits in the attiny261/461/861 and always read as zero. ? bit 2- pcke: pck enable the pcke bit change the timer/counter1 clock source. when it is set, the asynchronous clock mode is enabled and fast 64 mhz (or 32 mhz in low speed mode) pck clock is used as a timer/counter1 clock source. if this bit is cl eared, the synchronous clock mode is enabled, and system clock ck is used as timer/counter1 clock source. it is safe to set this bit only when the pll is locked i.e the plock bit is 1. note that the pcke bit can be set only, if the pll has been enabled earlier. the pll is enabled when t he cksel fuse has been programmed to 0x0001 (the pll clock mode is selected) or the plle bit has been set to one. ? bit 1- plle: pll enable when the plle is set, the pll is started and if needed internal rc-oscilla tor is started as a pll reference clock. if pll is sele cted as a system clock source th e value for this bit is always 1. ? bit 0- plock: pll lock detector when the plock bit is set, the pll is locked to the reference clock. the plock bit should be ignored during initial pll lock-in sequence when pll frequency overshoots and undershoots, before reaching steady state. the steady state is obtained within 100 s. after pll lock-in it is recommended to check the plock bit before enabling pck for timer/counter1. 15.1.2 tccr1b ? timer/coun ter1 control register b ? bit 7 - res: reserved bit ? bit 6 - psr1: prescaler reset timer/counter1 bit 76543210 0x29 (0x49)lsm----pckeplleplockpllcsr read/writer/wrrrrr/wr/wr initial value0000000/10 bit 76543210 0x2f (0x4f) - psr1 dtps11 dtps10 cs13 cs12 cs11 cs10 tccr1b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 91 7753f?avr?01/11 attiny261/attiny461/attiny861 when this bit is set (one), t he timer/counter prescaler (tcnt1 is unaffected) will be reset. the bit will be cleared by hard ware after the operation is performed. writing a zero to this bit will have no effect. this bit will always read as zero. ? bits 3:0 - cs13, cs12, cs11, cs10: clock select bits 3, 2, 1, and 0 the clock select bits 3, 2, 1, and 0 define the prescaling source of timer/counter1. the stop condition provides a timer enable/disable function. table 15-1. timer/counter1 pr escale select cs13 cs12 cs11 cs10 asynchronous clocking mode synchronous clocking mode 0 0 0 0 t/c1 stopped t/c1 stopped 0001pck ck 0010pck/2ck/2 0011pck/4ck/4 0100pck/8ck/8 0101pck/16ck/16 0110pck/32ck/32 0111pck/64ck/64 1000pck/128ck/128 1001pck/256ck/256 1010pck/512ck/512 1011pck/1024ck/1024 1100pck/2048ck/2048 1101pck/4096ck/4096 1110pck/8192ck/8192 1 1 1 1 pck/16384 ck/16384 92 7753f?avr?01/11 attiny261/attiny461/attiny861 16. timer/counter1 16.1 features ? 10/8-bit accuracy ? three independent output compare units ? clear timer on compare match (auto reload) ? glitch free, phase and frequency co rrect pulse width modulator (pwm) ? variable pwm period ? independent dead time generators for each pwm channels ? five independent interrupt sources (tov1, ocf1a, ocd1b, ocf1d, fpf1) ? high speed asynchronous and synchronous clocking modes ? separate prescaler unit 16.2 overview timer/counter1 is a general purpose high speed timer/counter module, with three independent output compare units, and with pwm support. the timer/counter1 features a high resolution and a high accuracy usage with the lower pres- caling opportunities. it can also support three accurate and high speed pulse width modulators using clock speeds up to 64 mhz. in pwm mode timer/counter1 and the output compare regis- ters serve as triple stand-alone pwms with non-overlapping non-inverted and inverted outputs. similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. a simplified block diagram of the timer/counter1 is shown in figure 16-1 . for actual placement of the i/o pins, refer to ?pinout attiny261/461/861? on page 2 . the device-specific i/o register and bit locations are listed in the ?register description? on page 115 . 93 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 16-1. timer/counter1 block diagram 16.2.1 speed the maximum speed of the timer/counter1 is 64 mhz. however, if a supply voltage below 2.7 volts is used, it is recommended to use the low speed mode (lsm), because the timer/counter1 is not running fast enough on low voltage levels. in the low speed mode the fast peripheral clock is scaled down to 32 mhz. for more details about the low speed mode, see ?pllcsr ? pll control and status register? on page 90 . 16.2.2 accuracy the timer/counter1 is a 10-bit timer/counter modu le that can alternatively be used as an 8-bit timer/counter. the timer/counter1 registers are bas ically 8-bit registers, but on top of that there is a 2-bit high byte register (tc1h) that can be used as a common temporary buffer to access the two msbs of the 10-bit timer/counte r1 registers by the avr cpu via the 8-bit data bus, if the 10-bit accuracy is used. whereas, if the two msbs of the 10-bit registers are written to zero the timer/counter1 is working as an 8-bit timer/counter. when reading the low byte of any 8-bit register the two msbs are written to the tc1h register, and when writing the low byte of any 8-bit register the two msbs are written from the tc1h register. special procedures must be followed when accessing the 10-bit timer/counter1 values via the 8-bit data bus. these proce- dures are described in the section ?accessing 10-bit registers? on page 112 . 8-bit databus t/c int. flag register (tifr) 10-bit comparator 8-bit output compare register a (ocr1a) t/c int. mask register (timsk) timer/counter1 (tcnt1) direction timer/counter1 control logic ocf1b tov1 toie1 ocie1b ocie1a ocf1a tov1 ocf1b oc1a ocf1a t/c control register a (tccr1a) com1b1 pwm1a pwm1b com1b0 foc1a foc1b 10-bit comparator 8-bit output compare register b (ocr1b) com1a1 com1a0 t/c control register b (tccr1b) cs12 psr1 cs11 cs10 cs13 oc1a oc1b oc1b dead time generator dead time generator 10-bit comparator 8-bit output compare register c (ocr1c) 10-bit comparator 8-bit output compare register d (ocr1d) com1a1 pwm1d com1a0 foc1d t/c control register c (tccr1c) ocf1d ocf1d ocie1d oc1d oc1d dead time generator psr1 psr1 ocw1a ocw1b ocw1d 2-bit high byte register (tc1h) wgm11 fpen1 t/c control register d (tccr1e) com1b1 com1b0 com1d1 com1d0 fpnc1 fpes1 fpac1 10-bit output compare register b 10-bit output compare register c 10-bit output compare register d 10-bit output compare register a clear count clk t/c control register c (tccr1d) fault_protection wgm10 fpie1 fpf1 oc1oe5 oc1oe4 oc1oe3 oc1oe2 oc1oe1 oc1oe0 fpie1 fpf1 94 7753f?avr?01/11 attiny261/attiny461/attiny861 16.2.3 registers the timer/counter (tcnt1) and output compare registers (ocr1a, ocr1b, ocr1c and ocr1d) are 8-bit registers that are used as a data source to be compared with the tcnt1 con- tents. the ocr1a, ocr1b and ocr1d registers determine the action on the oc1a, oc1b and oc1d pins and they can also generate the co mpare match interrupts. the ocr1c holds the timer/counter top value, i.e. the clear on compare match value. the timer/counter1 high byte register (tc1h) is a 2-bit register that is used as a common temporary buffer to access the msb bits of the timer/counter1 registers, if the 10-bit accuracy is used. interrupt request (overflow tov1, and compare matches ocf1a, ocf1b, ocf1d and fault pro- tection fpf1) signals are visible in the timer in terrupt flag register (tifr) and timer/counter1 control register d (tccr1d). the interrupts are individually masked with the timer interrupt mask register (timsk) and the fpie1 bit in the timer/counter1 control register d (tccr1d). control signals are found in the timer/counter control regi sters tccr1a, tccr1b, tccr1c, tccr1d and tccr1e. 16.2.4 synchronization in asynchronous clocking mode the timer/counter1 and the prescaler allow running the cpu from any clock source while the prescaler is opera ting on the fast peripheral clock (pck) having frequency of 64 mhz (or 32 mhz in low speed mode). this is possible because there is a syn- chronization boundary between the cpu clock domain and the fast peripheral clock domain. figure 16-2 shows timer/counter 1 synchronization register block diagram and describes syn- chronization delays in between registers. note that all clock gating details are not shown in the figure. the timer/counter1 register values go through the internal synchronization registers, which cause the input synchronization delay, before af fecting the counter operation. the registers tccr1a, tccr1b, tccr1c, tccr1d, ocr1a, ocr1b, ocr1c and ocr1d can be read back right after writing the register. the read back values are delayed for the timer/counter1 (tcnt1) register, timer/counter1 high byte register (tc1h) and flags (ocf1a, ocf1b, ocf1d and tov1), because of the input and output synchronization. the system clock frequency must be lower than half of the pck frequency, because the syn- chronization mechanism of the asynchronous time r/counter1 needs at least two edges of the pck when the system clock is high . if the frequency of th e system clock is too high, it is a risk that data or control values are lost. 95 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 16-2. timer/counter1 synchronization register block diagram. 16.2.5 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output com- pare unit, in this case compare unit a, b, c or d. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 counter value and so on. the definitions in table 16-1 are used extensively throughout the document. 8-bit databus ocr1a ocr1a_si tcnt1_so ocr1b ocr1b_si ocr1c ocr1c_si tccr1a tccr1a_si tccr1b tccr1b_si tcnt1 tcnt1_si ocf1a ocf1a_si ocf1b ocf1b_si tov1 tov1_si tov1_so ocf1b_so ocf1a_so tcnt1 s a s a pcke ck pck io-registers input synchronization registers timer/counter1 output synchronization registers sync mode async mode 1 ck delay 1/2 ck delay ~1/2 ck delay 1 pck delay 1 pck delay ~1 ck delay tcnt1 ocf1a ocf1b tov1 1/2 ck delay 1 ck delay ocr1d ocr1d_si tc1h tc1h_si tccr1c tccr1c_si tccr1d ocf1d ocf1d_si ocf1d_so ocf1d tc1h_so tc1h tccr1d_si table 16-1. definitions bottom the counter reaches the bottom when it becomes 0. max the counter reaches its maximum value when it becomes 0x3ff (decimal 1023). top the counter reaches the top value (stored in the ocr1c) when it becomes equal to the highest value in the count sequence. the top has a value 0x0ff as default after reset. 96 7753f?avr?01/11 attiny261/attiny461/attiny861 16.3 counter unit the main part of the timer/counter1 is the programmable bi-directional counter unit. figure 16-3 shows a block diagram of the counter and its surroundings. figure 16-3. counter unit block diagram signal description (internal signals): count tcnt1 increment or decrement enable. direction select between increment and decrement. clear clear tcnt1 (set all bits to zero). clk t n timer/counter clock, referred to as clk t1 in the following. top signalize that tcnt1 has reached maximum value. bottom signalize that tcnt1 has re ached minimum value (zero). depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t1 ). the timer clock is generated from an synchronous system clock or an asynchronous pll clock using the clock select bits (cs13:0) and the pck enable bit (pcke). when no clock source is selected (cs13:0 = 0) the timer is stopped. however, the tcnt1 value can be accessed by the cpu, regardless of whether clk t1 is present or not. a cpu write over- rides (has priority over) all counter clear or count operations. the counting sequence of the timer/counter1 is determined by the setting of the wgm10 and pwm1x bits located in the timer/counter1 control re gisters (tccr1a, tccr1c and tccr1d). for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 102 . the timer/counter overflow flag (tov1) is set according to the mode of operation selected by the pwm1x and wgm10 bits. the overflow flag can be used for generating a cpu interrupt. 16.3.1 counter initialization for asynchronous mode to change timer/counter1 to the asynchronous mode follow the procedure below: 1. enable pll. 2. wait 100 s for pll to stabilize. 3. poll the plock bit until it is set. 4. set the pcke bit in the pllcsr regist er which enables the asynchronous mode. data b u s tcnt1 control logic count tov1 top timer/counter1 count enable ( from prescaler ) bottom direction clear pck ck pcke clk t1 97 7753f?avr?01/11 attiny261/attiny461/attiny861 16.4 output compare unit the comparator continuously compares tcnt1 with the output compare registers (ocr1a, ocr1b, ocr1c and ocr1d). whenever tcnt1 equals to the output compare register, the comparator signals a match. a match will set the output compare flag (ocf1a, ocf1b or ocf1d) at the next timer clock cycle. if the corresponding interrupt is enabled, the output com- pare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternativel y, the flag can be cleared by software by writ- ing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the pwm1x, wgm10 and compare out- put mode (com1x1:0) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( see ?modes of operation? on page 102. ). figure 16-4 shows a block diagram of the output compare unit. figure 16-4. output compare unit, block diagram the ocr1x registers are double buffered when using any of the pulse width modulation (pwm) modes. for the normal mode of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr1x compare registers to either top or bottom of the counting sequence. the synchronization pr events the occurrence of odd-length, non-sym- metrical pwm pulses, thereby making the output glitch-free. see figure 16-5 for an example. during the time between the write and the update operation, a read from ocr1a, ocr1b, ocr1c or ocr1d will read the contents of the temporary location. this means that the most recently written value always will read out of ocr1a, ocr1b, ocr1c or ocr1d. ocfn x (int.req.) = (10-bit comparator ) 8-bit data bus tcntn wgm10 waveform generator comnx1:0 pwmnx tcnh ocwnx 10-bit tcntn 10-bit ocrnx ocrnx focn top bottom 98 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 16-5. effects of unsynchronized ocr latching 16.4.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force outp ut compare (foc1x) bit. forcin g compare match will not set the ocf1x flag or reload/cle ar the timer, but the wa veform output (ocw1x) will be updated as if a real compare match had occurred (the com1x1:0 bits settings define whether the waveform output (ocw1x) is set, cleared or toggled). 16.4.2 compare match bloc king by tcnt1 write all cpu write operations to the tcnt1 register will block any compare ma tch that occur in the next timer clock cycle, even when the timer is st opped. this feature allows ocr1x to be initial- ized to the same value as tcnt1 without triggering an interrupt when the timer/counter clock is enabled. 16.4.3 using the output compare unit since writing tcnt1 in any mode of operatio n will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt1 when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt1 equals the ocr1x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt1 value equal to bottom when the counter is down-counting. the setup of the waveform output (ocw1x) should be performed before setting the data direc- tion register for the port pin to output. the easiest way of setting the ocw1x value is to use the force output compare (foc1x) strobe bits in normal mode. the oc1x keeps its value even when changing between waveform generation modes. be aware that the com1x1:0 bits are not double buffered together with the compare value. changing the com1x1:0 bits will take effect immediately. output compare waveform ocwnx output compare wafeform ocwnx unsynchronized wfnx latch synchronized wfnx latch counter value compare value counter value compare value compare value changes glitch compare value changes 99 7753f?avr?01/11 attiny261/attiny461/attiny861 16.5 dead time generator the dead time generator is provided for the timer/counter1 pwm output pairs to allow driving external power control switches safely. the dead time generator is a separate block that can be used to insert dead times (non-overlapping times) for the timer/counter1 complementary output pairs oc1x and oc1x when the pwm mode is enabled and the com1x1:0 bits are set to ?01?. the sharing of tasks is as follows: the waveform generator generates the waveform out- put (ocw1x) and the dead time generator gener ates the non-overlapping pwm output pair from the waveform output. three dead time generators are provided, one for each pwm out- put. the non-overlap time is adjustable and the pwm output and it?s complementary output are adjusted separately, and independently for both pwm outputs. figure 16-6. output compare unit, block diagram the dead time generation is based on the 4- bit down counters that count the dead time, as shown in figure 16-7 . there is a dedicated prescaler in front of the dead time generator that can divide the timer/counter1 clock (pck or ck) by 1, 2, 4 or 8. this provides for large range of dead times that can be generated. the prescaler is controlled by two control bits dtps11..10. the block has also a rising and falling edge detector that is us ed to start the dea d time counting period. depending on the edge, one of the transitions on the rising edges, oc1x or oc1x is delayed until the counter has counted to zero. the comparator is used to compare the counter with zero and stop the dead time insertion when zero has been reached. the counter is loaded with a 4-bit dt1h or dt1l value from dt1 i/o register, depending on the edge of the waveform output (ocw1x) when the dead time insertion is started. the output compare output are delayed by one timer clock cycle at minimum from the waveform output when the dead time is adjusted to zero. the outputs oc1x and oc1x are inverted, if the pwm inversion mode bit pwm1x is set. this will also cause both outputs to be high during the dead time. figure 16-7. dead time generator ocnx pin wgm10 waveform generator top focn comnx bottom pwmnx ocwnx dead time generator ocnx pin dtnh dtnl dtpsn ck or pck clock ocnx ocnx clock control ocnx ocnx ck or pck clock ocwnx 4-bit counter comparator dtnl dtnh dead time pre-scaler dtpsn dtn i/o register data bus (8-bit) tccrnb register pwm1x pwm1x 100 7753f?avr?01/11 attiny261/attiny461/attiny861 the length of the counting period is user adjustable by selecting the dead time prescaler setting by using the dtps11:10 control bits, and selecting then the dead time value in i/o register dt1. the dt1 register consists of tw o 4-bit fields, dt1h and dt1l that control the dead time periods of the pwm output and its' complementary output separately in terms of the number of pres- caled dead time ge nerator clock cycles. thus the rising edge of oc1x and oc1x can have different dead time periods as the t non-overlap / rising edge is adjusted by the 4-bit dt1h value and the t non-overlap / falling edge is adjusted by the 4-bit dt1l value. figure 16-8. the complementary output pair, com1x1:0 = 1 16.6 compare match output unit the compare output mode (com1x1:0) bits have two functions. the waveform generator uses the com1x1:0 bits for defining the inverted or non-inverted waveform output (ocw1x) at the next compare match. also, the com1x1:0 bits control the oc1x and oc1x pin output source. figure 16-9 shows a simplified schematic of the logic affected by the com1x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com1x1:0 bits are shown. in normal mode (non-pwm) the dead time genera tor is disabled and it is working like a syn- chronizer: the output compare (oc1x) is delayed from the waveform output (ocw1x) by one timer clock cycle. whereas in fast pwm mode and in phase and frequency correct pwm mode when the com1x1:0 bits are set to ?01? both the non-inverted and the inverted output compare output are generated, and an user programmable dead time delay is inserted for these complementary output pairs (oc1x and oc1x ). the functionality in pwm modes is similar to normal mode when any other com1x1:0 bit setup is used. when referring to the oc1x state, the reference is for the output compare output (oc1x) from the dead time generator, not the oc1x pin. if a system reset occur, the oc1x is reset to ?0?. the general i/o port function is overridden by the output compare (oc1x / oc1x ) from the dead time generator if either of the com1x1:0 bits are set. however, the oc1x pin direction (input or output) is still controlled by the data di rection register (ddr) fo r the port pin. the data direction register bit for the oc1x and oc1x pins (ddr_oc1x and ddr_oc1x) must be set as output before the oc1x and oc1x values are visible on the pin. the port override function is independent of the output compare mode. ocnx (comnx = 1) t non-overlap / rising edge t non-overlap / falling edge ocnx ocwnx 101 7753f?avr?01/11 attiny261/attiny461/attiny861 the design of the output compare pin configuration logic allows initialization of the oc1x state before the output is enabled. note that some com1x1:0 bit settings are reserved for certain modes of operation. for output compare pin configurations refer to table 16-2 on page 103 , table 16-3 on page 105 , table 16-4 on page 107 , and table 16-5 on page 109 . figure 16-9. compare match output unit, schematic data b u s portb0 ddrb0 dq ddrb1 portb1 dq dq dq clk i/o portb2 ddrb2 d q ddrb3 portb3 d q d q d q portb4 ddrb4 dq ddrb5 portb5 dq dq dq 1 0 1 0 oc1d pin 2 1 0 dead time generator d q q ocw1d clk tn oc1d pin output compare pin configuration com1d1:0 wgm11 oc1oe5:4 1 0 1 0 1 0 oc1b pin 2 1 0 dead time generator b q q ocw1b clk tn oc1b pin output compare pin configuration com1b1:0 wgm11 oc1oe3:2 1 0 1 0 oc1a pin 0 1 dead time generator a q q ocw1a clk tn oc1a pin output compare pin configuration com1a1:0 wgm11 oc1oe1:0 1 0 oc1a oc1a oc1b oc1b oc1d oc1d 102 7753f?avr?01/11 attiny261/attiny461/attiny861 16.6.1 compare output mode and waveform generation the waveform generator uses the com1x1:0 bits differently in normal mode and pwm modes. for all modes, setting the com1x1:0 = 0 tells the waveform generator that no action on the ocw1x output is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 16-6 on page 115 . for fast pwm mode, refer to table 16-7 on page 115 , and for the phase and frequency correct pwm refer to table 16-8 on page 116 . a change of the com1x1:0 bits state will have effe ct at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc1x strobe bits. 16.7 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (bits pwm1x and wgm10) and compare output mode (com1x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generati on mode bits do. the com1x1:0 bits control whether the pwm output generated should be inverted, non-inverted or complementary. for non-pwm modes the com1x1:0 bits control whether the output should be set, cleared, or tog- gled at a compare match. 16.7.1 normal mode the simplest mode of operation is the normal mode (pwm1x = 0), the counter counts from bottom to top (defined as ocr1c) then restarts from bottom. the ocr1c defines the top value for the counter, hence also its resolution, and allows control of the compare match output frequency. in toggle compare output mode the waveform output (ocw1x) is toggled at compare match between tcnt1 and ocr1x. in non-inverting compare output mode the waveform output is cleared on the compare match. in inverting compare output mode the waveform output is set on compare match. the timing diagram for the normal mode is shown in figure 16-10 . the counter value (tcnt1) that is shown as a histogram in the timing diagram is incremented until the counter value matches the top value. the counter is then cleared at the following clock cycle the diagram includes the waveform output (ocw1x) in toggle compare mode. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. figure 16-10. normal mode, timing diagram tcntn ocwnx (comnx=1) ocnx interrupt flag set 1 4 period 2 3 tovn interrupt flag set 103 7753f?avr?01/11 attiny261/attiny461/attiny861 the timer/counter overflow flag (tov1) is se t in the same clock cycle as the tcnt1 becomes zero. the tov1 flag in this case behaves like a 11t h bit, except that it is only set, not cleared. however, combined with the timer overflow inte rrupt, that automatically clears the tov1 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. for generating a waveform, the ocw1x output can be set to toggle its logical level on each compare match by setting the compare output mode bits to tog- gle mode (com1x1:0 = 1). the oc1x value will not be visible on the port pin unless the data direction for the pin is set to output. the wa veform generated will have a maximum frequency of f oc1x = f clkt1 /4 when ocr1c is set to zero. the waveform frequency is defined by the following equation: resolution shows how many bit is required to express the value in the ocr1c register. it is cal- culated by following equation: resolution pwm = log 2 (ocr1c + 1). the output compare pin configurations in normal mode are described in table 16-2 . 16.7.2 fast pwm mode the fast pulse width modulation or fast pwm mode (pwm1x = 1 and wgm10 = 0) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to top (defined as ocr1c) then restarts from bottom. in non-inverting compare output mode the waveform output (ocw1x) is cleared on the compare match between tcnt1 and ocr1x and set at bottom. in inverting compare output mode, the waveform output is set on compare match and cleared at bottom. in complementary compare output mode the waveform output is cleared on the compare match and set at bottom. due to the single-slope operation, the operatin g frequency of the fast pwm mode can be twice as high as the phase and frequency correct pwm mode that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physicall y small sized external components (coils, capacitors), and therefore reduces total system cost. the timing diagram for the fast pwm mode is shown in figure 16-11 . the counter is incre- mented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the tcnt1 value is in the timing diagram shown as a histogram for illustrating the sing le-slope operation. table 16-2. output compare pin configurations in normal mode com1x1 com1x0 oc1x pin oc1x pin 0 0 disconnected disconnected 0 1 disconnected oc1x 1 0 disconnected oc1x 1 1 disconnected oc1x f oc 1 x f clkt1 21 ocr 1 c + () ? --------------------------------------------- = 104 7753f?avr?01/11 attiny261/attiny461/attiny861 the diagram includes the waveform output in non-inverted and inverted compare output modes. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. figure 16-11. fast pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time the counter reaches top. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc1x pins. setting the com1x1:0 bits to two will produce a non-inverted pwm and se tting the com1x1:0 to three will produce an inverted pwm output. setting the com1x1:0 bits to one will enable com- plementary compare output mode and produce both the non-inverted (oc1x) and inverted output (oc1x ). the actual value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by setting (or clearing) the waveform output (ocw1x) at the compare match between ocr1x and tcnt1, and clearing (or setting) the waveform output at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the number of steps in single-slope operation. the value of n equals either to the top value. the extreme values for the ocr1c register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr1c is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr1c equal to max will result in a constantly high or low output (depending on the polarity of the output set by the com1x1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by set- ting the waveform output (ocw1x) to toggle its logical level on each compare match (com1x1:0 = 1). the waveform generate d will have a maximum frequency of f oc1 = f clkt1 /4 when ocr1c is set to three. tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocwnx ocwnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 f ocnxpwm f clkt1 n ------------ - = 105 7753f?avr?01/11 attiny261/attiny461/attiny861 the general i/o port function is overridden by the output compare value (oc1x / oc1x ) from the dead time generator, if either of the com1x1:0 bits are set and the data direction register bits for the oc1x and oc1x pins are set as an output. if the com1x1:0 bits are cleared, the actual value from the port regist er will be visible on the port pin. the output compare pin config- urations are described in table 16-3 . 16.7.3 phase and frequency correct pwm mode the phase and frequency correct pwm mode (pwmx = 1 and wgm10 = 1) provides a high resolution phase and frequency correct pwm waveform generation option. the phase and frequency correct pwm mode is based on a dual-slope operation. the counter counts repeat- edly from bottom to top (defined as ocr1c) and then from top to bottom. in non-inverting compare output mode the waveform output (ocw1x) is cleared on the compare match between tcnt1 and ocr1x while upcounting, and set on the compare match while down-counting. in inverting output compare mode, the operation is inverted. in complementary compare output mode, the waveform output is cleared on the compare match and set at bot- tom. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feat ure of the dual-slope pwm modes, these modes are preferred for motor control applications. the timing diagram for the phase and frequency correct pwm mode is shown on figure 16-12 in which the tcnt1 value is shown as a histogra m for illustrating the dua l-slope operation. the counter is incremented until the counter value matches top. when the counter reaches top, it changes the count direction. the tcnt1 value w ill be equal to top for one timer clock cycle. the diagram includes the waveform output (ocw1x) in non-inverted and inverted compare output mode. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. table 16-3. output compare pin configurations in fast pwm mode com1x1 com1x0 oc1x pin oc1x pin 0 0 disconnected disconnected 01oc1x oc1x 1 0 disconnected oc1x 1 1 disconnected oc1x 106 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 16-12. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in the phase and frequency correct pwm mode, the compare unit allows generation of pwm waveforms on the oc1x pins. setting the com1 x1:0 bits to two will produce a non-inverted pwm and setting the com1 x1:0 to three will produce an in verted pwm output. setting the com1a1:0 bits to one will enable complementary compare ou tput mode and produce both the non-inverted (oc1x) and inverted output (oc1x ). the actual values will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the waveform output (ocw1x) at the compare match between ocr1x and tcnt1 when the counter increments, and setting (or clearing) the waveform output at compare match when the counter decrements. the pwm fr equency for the output when using the phase and frequency correct pwm can be calculated by the following equation: the n variable represents the number of steps in dual-slope operation. the value of n equals to the top value. the extreme values for the ocr1c register represent special cases when generating a pwm waveform output in the phase and frequency correct pwm mode. if the ocr1c is set equal to bottom, the output will be continu ously low and if set equal to max the output will be continu- ously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. the general i/o port function is overridden by the output compare value (oc1x / oc1x ) from the dead time generator, if either of the com1x1:0 bits are set and the data direction register bits for the oc1x and oc1x pins are set as an output. if the com1x1:0 bits are cleared, the actual value from the port register will be visible on the port pin. the conf igurations of the output compare pins are described in table 16-4 . tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocwnx ocwnx (comnx = 2) (comnx = 3) ocrnx update f ocnxpcpwm f clkt1 n ------------ - = 107 7753f?avr?01/11 attiny261/attiny461/attiny861 16.7.4 pwm6 mode the pwm6 mode (pwm1a = 1, wgm11 = 1 and wgm10 = x) provide pwm waveform genera- tion option e.g. for controlling brushless dc (bldc) motors. in the pwm6 mode the ocr1a register controls all six output compare waveforms as the same waveform output (ocw1a) from the waveform generator is used for generating all waveforms. the pwm6 mode also pro- vides an output compare override enable regi ster (oc1oe) that can be used with an instant response for disabling or enabling the output compare pins. if the output compare override enable bit is cleared, the actual value from the port register will be visible on the port pin. the pwm6 mode provides two counter operat ion modes, a single-slope operation and a dual-slope operation. if the single-slope operation is selected (the wgm10 bit is set to 0), the counter counts from bottom to top (defined as ocr1c) then restart from bottom like in fast pwm mode. the pwm waveform is generated by setting (or clearing) the waveform out- put (ocw1a) at the compare match between ocr1a and tcnt1, and clearing (or setting) the waveform output at the timer clock cycle the counter is cleared (changes from top to bot- tom). the timer/counter overflow flag (tov1) is set each time the c ounter reaches the top and, if the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. whereas, if the dual-slope operation is selected (the wgm10 bit is set to 1), the counter counts repeatedly from bottom to top (defined as ocr1c) and then from top to bottom like in phase and frequency correct pwm mode. the pwm waveform is generated by setting (or clearing) the waveform output (ocw1a) at the compare match between ocr1a and tcnt1 when the counter increments, and clearing (or setting) the waveform output at the he compare match between ocr1a and tcnt1 when the coun ter decrements. the timer/counter overflow flag (tov1) is set each time the counter reaches the bottom and, if the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. the timing diagram for the pwm6 mode in single-slope operation (wgm11 = 0) when the com1a1:0 bits are set to ?10? is shown in figure 16-13 . the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the tcnt1 value is in the timing diagram shown as a histogram for illustrating the sin- gle-slope operation. the timing diagram includes output compare pins oc1a and oc1a, and the corresponding output compare override enable bits (oc1oe1..oc1oe0). table 16-4. output compare pin configurations in phase and frequency correct pwm mode com1x1 com1x0 oc1x pin oc1x pin 0 0 disconnected disconnected 01oc1x oc1x 1 0 disconnected oc1x 1 1 disconnected oc1x 108 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 16-13. pwm6 mode, single-slope operation, timing diagram the general i/o port function is overridden by the output compare value (oc1x / oc1x ) from the dead time generator if either of the com1x1:0 bits are set. the output compare pins can also be overridden by the output compare override enable bits oc1oe5..oc1oe0. if an over- ride enable bit is cleared, the actual value from the port register will be visible on the port pin and, if the override enable bit is set, the output compare pin is allowed to be connected on the port pin. the output compare pin configurations are described in table 16-5 . tcnt1 oc1a pin oc1a pin oc1b pin oc1b pin oc1d pin oc1d pin oc1oe0 oc1oe1 oc1oe2 oc1oe3 oc1oe4 oc1oe5 ocw1a 109 7753f?avr?01/11 attiny261/attiny461/attiny861 16.8 timer/counter timing diagrams the timer/counter is a synchron ous design and the timer clock (clk t1 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 16-14 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase and frequency correct pwm mode. figure 16-15 shows the same timing data, but with the prescaler enabled, in all modes other than phase and frequency correct pwm mode. figure 16-16 shows the setting of ocf1a, ocf1b and ocf1d in all modes, and figure 16-17 shows the setting of tov1 in phase and frequency correct pwm mode. figure 16-14. timer/counter timing diagram, no prescaling table 16-5. output compare pin configurations in pwm6 mode com1a1 com1a0 oc1a pin (pb0) oc1a pin (pb1) 0 0 disconnected disconnected 01oc1a ? oc1oe0 oc1a ? oc1oe1 10oc1a ? oc1oe0 oc1a ? oc1oe1 11oc1a ? oc1oe0 oc1a ? oc1oe1 com1b1 com1b0 oc1b pin (pb2) oc1b pin (pb3) 0 0 disconnected disconnected 01oc1a ? oc1oe2 oc1a ? oc1oe3 10oc1a ? oc1oe2 oc1a ? oc1oe3 11oc1a ? oc1oe2 oc1a ? oc1oe3 com1d1 com1d0 oc1d pin (pb4) oc1d pin (pb5) 0 0 disconnected disconnected 01oc1a ? oc1oe4 oc1a ? oc1oe5 10oc1a ? oc1oe4 oc1a ? oc1oe5 11oc1a ? oc1oe4 oc1a ? oc1oe5 clk tn (clk pck /1) tovn clk pck tcntn top - 1 top bottom bottom + 1 110 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 16-15. timer/counter timing dia gram, with prescaler (f clkt1 /8) figure 16-16. timer/counter timing diagram, setting of ocf1x, with prescaler (f clkt1 /8) figure 16-17. timer/counter timing dia gram, with prescaler (f clkt1 /8) tovn tcntn top - 1 top bottom bottom + 1 clk pck clk tn (clk pck /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk pck clk tn (clk pck /8) tovn tcntn bottom + 1 bottom + 1 bottom bottom + 1 clk pck clk tn (clk pck /8) 111 7753f?avr?01/11 attiny261/attiny461/attiny861 16.9 fault protection unit the timer/counter1 incorporates a fault protection unit that can disable the pwm output pins, if an external event is triggered. the external signal indicating an event can be applied via the external interrupt int0 pin or alternatively, via the analog-comparator unit. the fault protection unit is illustrated by th e block diagram shown in figure 16-18 . the elements of the block diagram that are not directly a part of the fault protection unit are gray shaded. figure 16-18. fault protection unit block diagram when the fault protection mode is enabled by the fault protection enable (fpen1) bit and a change of the logic level (an event) occurs on the external interrupt pin (int0), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge detec- tor, a fault protection mode will be triggered. when a fault protection is triggered, the com1x bits are cleared, output comparators are disconnected from the pwm output pins and the portb register bits are connected on the pwm output pins. the fault protection enable (fpen1) is automatically cleared at the same system clock as the com1nx bits are cleared. if the fault protection interrupt enable bit (fpie1) is set, a fault protection interrupt is generated and the fpen1 bit is cleared. alternatively the fpen1 bit can be polled by software to figure out when the timer/counter has entered to fault protection mode. 16.9.1 fault protection trigger source the main trigger source for the fault protection unit is the external interrupt pin (int0). alterna- tively the analog comparator output can be used as trigger source for the fault protection unit. the analog comparator is selected as trigger source by setting the fault protection analog comparator (fpac1) bit in the timer/counter1 control register (tccr1d). be aware that changing trigger source can trigger a fault protection mode. therefore it is recommended to clear the fpf1 flag after changing trigger sour ce, setting edge detector or enabling the fault protection. both the external interrupt pin (int0) and the analog comparator output (aco) inputs are sam- pled using the same technique as for the t0 pin ( figure 13-1 on page 70 ). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increase s the delay by four system cloc k cycles. an input capture can also be triggered by software by controlling the port of the int0 pin. 16.9.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the fault protection noise canceler (fpnc1) bit in timer/counter1 control register d (tccr1d ). when enabled the noise canceler introduces additional four system cloc k cycles of delay from a change applied to the input. the noise can- celer uses the system clock and is therefore not affected by the prescaler. analog comparator noise canceler int0 edge detector fpac1 fpnc1 fpes1 aco* fpen1 timer/counter1 fault_protection (int. req.) 112 7753f?avr?01/11 attiny261/attiny461/attiny861 16.10 accessing 10-bit registers if 10-bit values are written to the tcnt1 and ocr1a/b/c/d registers, the 10-bit registers can be byte accessed by the avr cpu via the 8-bit da ta bus using two read or write operations. the 10-bit registers have a common 2-bit timer/counter1 high byte register (tc1h) that is used for temporary storing of the two msbs of the 10-bi t access. the same tc1h register is shared between all 10-bit registers. accessing the low byte triggers the 10-bit read or write operation. when the low byte of a 10-bit register is written by the cpu, the high byte stored in the tc1h register, and the low byte written are both copied into the 10-bit register in the same clock cycle. when the low byte of a 10-bit register is read by the cpu, the high byte of the 10-bit register is copied into the tc1h register in the same clock cycle as the low byte is read. to do a 10-bit write, the high byte must be written to the tc1h register before the low byte is written. for a 10-bit read, the low byte must be read before the high byte. the following code examples show how to access the 10-bit timer registers assuming that no interrupts updates the tc1h register. the same pr inciple can be used directly for accessing the ocr1a/b/c/d registers. note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt1 value in the r17:r16 register pair. assembly code example ... ; set tcnt 1 to 0x01ff ldi r17,0x01 ldi r16,0xff out tc 1 h,r17 out tcnt 1 ,r16 ; read tcnt 1 into r17:r16 in r16,tcnt 1 in r17,tc 1 h ... c code example unsigned int i; ... /* set tcnt1 to 0x01ff */ tc1h = 0x01; tcnt1 = 0xff; /* read tcnt1 into i */ i = tcnt1; i |= (( unsigned int )tc1h << 8); ... 113 7753f?avr?01/11 attiny261/attiny461/attiny861 it is important to notice that accessing 10-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 10-bit register, and the interrupt code updates the tc1h register by accessing the same or any other of the 10-bit timer registers, then the result of the access outside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the tc1h regi ster, the main code must disable the interrupts during the 16-bit access. the following code examples show how to do an atomic read of the tcnt1 register contents. reading any of the ocr1a/b/c/d registers can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt1 value in the r17:r16 register pair. assembly code example tim1_readtcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt 1 into r17:r16 in r16,tcnt 1 in r17,tc 1 h ; restore global interrupt flag out sreg,r18 ret c code example unsigned int tim1_readtcnt1( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt1 into i */ i = tcnt1; i |= ((unsigned int)tc1h << 8); /* restore global interrupt flag sreg = sreg; return i; } 114 7753f?avr?01/11 attiny261/attiny461/attiny861 the following code examples show how to do an atomic write of the tcnt1 register contents. writing any of the ocr1a/b/c/d registers can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to tcnt1. 16.10.1 reusing the temporary high byte register if writing to more than one 10-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. assembly code example tim1_writetcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt 1 to r17:r16 out tc 1 h,r17 out tcnt 1 ,r16 ; restore global interrupt flag out sreg,r18 ret c code example void tim1_writetcnt1( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt1 to i */ tc1h = (i >> 8); tcnt1 = (unsigned char)i; /* restore global interrupt flag */ sreg = sreg; } 115 7753f?avr?01/11 attiny261/attiny461/attiny861 16.11 register description 16.11.1 tccr1a ? timer/counter1 control register a ? bits 7,6 - com1a1, com1a0: comparator a output mode, bits 1 and 0 these bits control the behavior of the wave form output (ocw1a) and the connection of the output compare pin (oc1a). if one or both of the com1a1:0 bits are set, the oc1a output overrides the normal port functionality of the i/o pin it is connected to. the complementary oc1b output is connected only in pwm modes when the com1a1:0 bits are set to ?01?. note that the data direction register (d dr) bit corresponding to the oc1a and oc1a pins must be set in order to enable the output driver. the function of the com1a1:0 bits depends on the pwm1a, wgm10 and wgm11 bit settings. table 16-6 shows the com1a1:0 bit functionality when the pwm1a bit is set to normal mode (non-pwm). table 16-7 shows the com1a1:0 bit functionality when the pwm1a, wgm10 and wgm11 bits are set to fast pwm mode. bit 76543210 0x30 (0x50) com1a1 com1a0 com1b1 com1b0 foc1a foc1b pwm1a pwm1b tccr1a read/write r/w r/w r/w r/w w w r/w r/w initial value00000000 table 16-6. compare output mode, normal mode (non-pwm) com1a1..0 ocw1a behavior oc1a pin oc1a pin 00 normal port operation. disconnected disconnected 01 toggle on compare match. connected disconnected 10 clear on compare match. connected disconnected 11 set on compare match. connected disconnected table 16-7. compare output mode, fast pwm mode com1a1..0 ocw1a behavior oc1a oc1a 00 normal port operation. disconnected disconnected 01 cleared on compare match. set when tcnt1 = 0x000. connected connected 10 cleared on compare match. set when tcnt1 = 0x000. connected disconnected 11 set on compare match. cleared when tcnt1 = 0x000. connected disconnected 116 7753f?avr?01/11 attiny261/attiny461/attiny861 table 16-8 shows the com1a1:0 bit functionality when the pwm1a, wgm10 and wgm11 bits are set to phase and frequency correct pwm mode. table 16-9 shows the com1a1:0 bit functionality when the pwm1a, wgm10 and wgm11 bits are set to single-slope pwm6 mode. in the pwm6 mode the same waveform output (ocw1a) is used for generating all waveforms and the output compare values oc1a and oc1a are con- nected on the all oc1x and oc1x pins as described below. table 16-10 shows the com1a1:0 bit functionality when the pwm1a, wgm10 and wgm11 bits are set to dual-slope pwm6 mode.i ? bits 5,4 - com1b1, com1b0: comparator b output mode, bits 1 and 0 these bits control the behavior of the waveform output (ocw1b) and the connection of the output compare pin (oc1b). if one or both of the com1b1:0 bits are set, the oc1b output overrides the normal port functionality of the i/o pin it is connected to. the complementary oc1b output is connected only in pwm modes when the com1b1:0 bits are set to ?01?. table 16-8. compare output mode, phase and frequency correct pwm mode com1a1..0 ocw1a behavior oc1a pin oc1a pin 00 normal port operation. disconnected disconnected 01 cleared on compare match when up-counting. set on compare match when down-counting. connected connected 10 cleared on compare match when up-counting. set on compare match when down-counting. connected disconnected 11 set on compare match when up-counting. cleared on compare match when down-counting. connected disconnected table 16-9. compare output mode, single-slope pwm6 mode com1a1..0 ocw1a behavior oc1x pin oc1x pin 00 normal port operation. disconnected disconnected 01 cleared on compare match. set when tcnt1 = 0x000. oc1a oc1a 10 cleared on compare match. set when tcnt1 = 0x000. oc1a oc1a 11 set on compare match. cleared when tcnt1 = 0x000. oc1a oc1a table 16-10. compare output mode, dual-slope pwm6 mode com1a1..0 ocw1a behavior oc1x pin oc1x pin 00 normal port operation. disconnected disconnected 01 cleared on compare match when up-counting. set on compare match when down-counting. oc1a oc1a 10 cleared on compare match when up-counting. set on compare match when down-counting. oc1a oc1a 11 set on compare match when up-counting. cleared on compare match when down-counting. oc1a oc1a 117 7753f?avr?01/11 attiny261/attiny461/attiny861 note that the data direction register (ddr) bit corresponding to the oc1b pin must be set in order to enable the output driver. the function of the com1b1:0 bits depends on the pwm1b and wgm10 bit settings. table 16-11 shows the com1b1:0 bit functionality when the pwm1b bit is set to normal mode (non-pwm). table 16-12 shows the com1b1:0 bit functionality when the pwm1b and wgm10 bits are set to fast pwm mode. table 16-13 shows the com1b1:0 bit functionality when the pwm1b and wgm10 bits are set to phase and frequency correct pwm mode. ? bit 3 - foc1a: force output compare match 1a the foc1a bit is only active when the pwm1a bit specify a non-pwm mode. writing a logical one to this bit forces a change in the waveform output (ocw1a) and the out- put compare pin (oc1a) according to the values already set in com1a1 and com1a0. if com1a1 and com1a0 written in the same cycle as foc1a, the new settings will be used. the force output compare bit can be used to change the output pin value regardless of the timer value. table 16-11. compare output mode, normal mode (non-pwm) com1b1..0 ocw1b behavior oc1b pin oc1b pin 00 normal port operation. disconnected disconnected 01 toggle on compare match. connected disconnected 10 clear on compare match. connected disconnected 11 set on compare match. connected disconnected table 16-12. compare output mode, fast pwm mode com1b1..0 ocw1b behavior oc1b pin oc1b pin 00 normal port operation. disconnected disconnected 01 cleared on compare match. set when tcnt1 = 0x000. connected connected 10 cleared on compare match. set when tcnt1 = 0x000. connected disconnected 11 set on compare match. cleared when tcnt1 = 0x000. connected disconnected table 16-13. compare output mode, phase and frequency correct pwm mode com1b1..0 ocw1b behavior oc1b pin oc1b pin 00 normal port operation. disconnected disconnected 01 cleared on compare match when up-counting. set on compare match when down-counting. connected connected 10 cleared on compare match when up-counting. set on compare match when down-counting. connected disconnected 11 set on compare match when up-counting. cleared on compare match when down-counting. connected disconnected 118 7753f?avr?01/11 attiny261/attiny461/attiny861 the automatic action programmed in com1a1 and com1a0 takes place as if a compare match had occurred, but no interrupt is generated. the foc1a bit is always read as zero. ? bit 2 - foc1b: force output compare match 1b the foc1b bit is only active when the pwm1b bit specify a non-pwm mode. writing a logical one to this bit forces a change in the waveform output (ocw1b) and the out- put compare pin (oc1b) according to the values already set in com1b1 and com1b0. if com1b1 and com1b0 written in the same cycle as foc1b, the new settings will be used. the force output compare bit can be used to change the output pin value regardless of the timer value. the automatic action programmed in com1b1 and com1b0 takes place as if a compare match had occurred, but no interrupt is generated. the foc1b bit is always read as zero. ? bit 1 - pwm1a: pulse width modulator a enable when set (one) this bit enables pwm mode based on comparator ocr1a ? bit 0 - pwm1b: pulse width modulator b enable when set (one) this bit enables pwm mode based on comparator ocr1b. 16.11.2 tccr1b ? timer/counter1 control register b ? bit 7 - pwm1x: pwm inversion mode when this bit is set (one), the pwm inversion mode is selected and the dead time generator outputs, oc1x and oc1x are inverted. ? bit 6 - psr1: prescaler reset timer/counter1 when this bit is set (one), the timer/counter1 pr escaler (tcnt1 is unaffe cted) will be reset. the bit will be cleared by hard ware after the operation is performed. writing a zero to this bit will have no effect. this bit will always read as zero. ? bits 5,4 - dtps11, dtps10: dead time prescaler bits the timer/counter1 control register b is a 8-bit read/write register. the dedicated dead time prescaler in front of the dead time generator can divide the timer/counter1 clock (pck or ck) by 1, 2, 4 or 8 providing a large range of dead times that can be generated. the dead time prescaler is controlled by two bits dtps11 and dtps10 from the dead time prescaler register. these bits define the division factor of the dead time prescaler. the division factors are given in table 16-14 . bit 76543210 0x2f (0x4f) pwm1x psr1 dtps11 dtps10 cs13 cs12 cs11 cs10 tccr1b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 119 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bits 3.. 0 - cs13, cs12, cs11, cs10: clock select bits 3, 2, 1, and 0 the clock select bits 3, 2, 1, and 0 define the prescaling source of timer/counter1. the stop condition provides a timer enable/disable function. 16.11.3 tccr1c ? timer/counter1 control register c ? bits 7,6 - com1a1s, com1 a0s: comparator a output mode, bits 1 and 0 these bits are the shadow bits of the com1a1 and com1a0 bits that are described in the sec- tion ?tccr1a ? timer/counter1 control register a? on page 115 . table 16-14. division factors of the dead time prescaler dtps11 dtps10 prescaler divi des the t/c1 clock by 0 0 1x (no division) 012x 104x 118x table 16-15. timer/counter1 prescaler select cs13 cs12 cs11 cs10 asynchronous clocking mode synchronous clocking mode 0000t/c1 stopped t/c1 stopped 0001pck ck 0010pck/2 ck/2 0011pck/4 ck/4 0100pck/8 ck/8 0101pck/16 ck/16 0110pck/32 ck/32 0111pck/64 ck/64 1000pck/128 ck/128 1001pck/256 ck/256 1010pck/512 ck/512 1011pck/1024 ck/1024 1100pck/2048 ck/2048 1101pck/4096 ck/4096 1110pck/8192 ck/8192 1111pck/1 6384 ck/16384 bit 76543210 0x27 (0x47) com1a1s com1a0s com1b1s com1b0s com1d1 com1d0 foc1d pwm1d tccr1c read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 120 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bits 5,4 - com1b1s, com1 b0s: comparator b output mode, bits 1 and 0 these bits are the shadow bits of the com1a1 and com1a0 bits that are described in the sec- tion ?tccr1a ? timer/counter1 control register a? on page 115 . ? bits 3,2 - com1d1, com1d0: comparator d output mode, bits 1 and 0 these bits control the behavior of the waveform output (ocw1d) and the connection of the output compare pin (oc1d). if one or both of the com1d1:0 bits are set, the oc1d output overrides the normal port functionality of the i/o pin it is connected to. the complementary oc1d output is connected only in pwm modes when the com1d1:0 bits are set to ?01?. note that the data direction register (ddr) bit corres ponding to the oc1d pin must be set in order to enable the output driver. the function of the com1d1:0 bits depends on the pwm1d and wgm10 bit settings. table 16-16 shows the com1d1:0 bit functionality when the pwm1d bit is set to a normal mode (non-pwm). table 16-17 shows the com1d1:0 bit functionality when the pwm1d and wgm10 bits are set to fast pwm mode. table 16-18 on page 121 shows the com1d1:0 bit functionality when the pwm1d and wgm10 bits are set to phase and frequency correct pwm mode. table 16-16. compare output mode, normal mode (non-pwm) com1d1..0 ocw1d behavior oc1d pin oc1d pin 00 normal port operation. disconnected disconnected 01 toggle on compare match. connected disconnected 10 clear on compare match. connected disconnected 11 set on compare match. connected disconnected table 16-17. compare output mode, fast pwm mode com1d1..0 ocw1d behavior oc1d pin oc1d pin 00 normal port operation. disconnected disconnected 01 cleared on compare match. set when tcnt1 = 0x000. connected connected 10 cleared on compare match. set when tcnt1 = 0x000. connected disconnected 11 set on compare match. clear when tcnt1 = 0x000. connected disconnected 121 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bit 1 - foc1d: force output compare match 1d the foc1d bit is only active when the pwm1d bit specify a non-pwm mode. writing a logical one to this bit forces a change in the waveform output (ocw1d) and the out- put compare pin (oc1d) according to the values already set in com1d1 and com1d0. if com1d1 and com1d0 written in the same cycle as foc1d, th e new settings will be used. the force output compare bit can be used to change the output pin value regardless of the timer value. the automatic action programmed in com1d1 and com1d0 takes place as if a compare match had occurred, but no interrupt is generated. the foc1d bit is always read as zero. ? bit 0 - pwm1d: pulse width modulator d enable when set (one) this bit enables pwm mode based on comparator ocr1d. 16.11.4 tccr1d ? timer/counter1 control register d ? bit 7 - fpie1: fault protection interrupt enable setting this bit (to one) enables the fault protection interrupt. ? bit 6? fpen1: fault protection mode enable setting this bit (to one) activates the fault protection mode. ? bit 5 ? fpnc1: fault protection noise canceler setting this bit activates the fault protection no ise canceler. when the noi se canceler is acti- vated, the input from the fault protection pin (int0) is filtered. the filter function requires four successive equal valued samples of the int0 pin for changing its output. the fault protection is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 4 ? fpes1: fault protection edge select this bit selects which edge on the fault protecti on pin (int0) is used to trigger a fault event. when the fpes1 bit is written to zero, a falling (negative) edge is used as trigger, and when the fpes1 bit is written to one, a rising (positive) edge will trigger the fault. table 16-18. compare output mode, phase and frequency correct pwm mode com1d1..0 ocw1d behavior oc1d pin oc1d pin 00 normal port operation. disconnected disconnected 01 cleared on compare match when up-counting. set on compare match when down-counting. connected connected 10 cleared on compare match when up-counting. set on compare match when down-counting. connected disconnected 11 set on compare match when up-counting. cleared on compare match when down-counting. connected disconnected bit 76543210 0x26 (0x46) fpie1 fpen1 fpnc1 fpes1 fpac1 fpf1 wgm11 wgm10 tccr1d read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 122 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bit 3 - fpac1: fault protection analog comparator enable when written logic one, this bit enables the fault protection function in timer/counter1 to be triggered by the analog comparator. the comparator output is in this case directly connected to the fault protection front-end logic, making the comparator utilize the noise canceler and edge select features of the timer/counter1 fault protection interrupt. when written logic zero, no con- nection between the analog comparator and the fault protection function exists. to make the comparator trigger the timer/counter1 fault protection interrupt, the fpie1 bit in the timer/counter1 control regist er d (tccr1d) must be set. ? bit 2- fpf1: fault protection interrupt flag when the fpie1 bit is set (one), the fault protec tion interrupt is enabled. activity on the pin will cause an interrupt request even, if the fault protec tion pin is configured as an output. the corre- sponding interrupt of fault protection interrupt request is executed from the fault protection interrupt vector. the bit fpf1 is cleared by hardware when executing the corresponding inter- rupt handling vector. alternatively, fpf1 is clea red after a synchronization clock cycle by writing a logical one to the flag. when the sreg i-bit, fpie1 and fpf1 are set, the fault interrupt is executed. ? bits 1:0 - wgm11, wgm10: waveform generation mode bits this bit associated with the pwmx bits control the counting sequence of the counter, the source for type of waveform generation to be used, see table 16-19 . modes of operation supported by the timer/counter1 are: normal mode (counter), fast pwm mode, phase and frequency cor- rect pwm and pwm6 modes. 16.11.5 tccr1e ? timer/counter1 control register e ? bits 7:6 - res: reserved bits these bits are reserved bits in the attiny261/461/861 and always reads as zero. ? bits 5:0 ? oc1oe5:oc1oe0: output compare override enable bits these bits are the output compare override enable bits that are used to connect or disconnect the output compare pins in pwm6 modes with an instant response on the corresponding out- put compare pins. table 16-19. waveform generation mode bit description pwm1x wgm11..10 timer/counter mode of operation top update of ocr1x at tov1 flag set on 0 xx normal ocr1c immediate top 1 00 fast pwm ocr1c top top 1 01 phase and frequency correct pwm ocr1c bottom bottom 1 10 pwm6 / single-slope ocr1c top top 1 11 pwm6 / dual-slope ocr1c bottom bottom bit 76543210 0x00 (0x20) - - oc1oe5 oc1oe4 oc1oe3 oc 1oe2 oc1oe1 oc1oe0 tccr1e read/write r r r/w r/w r/w r/w r/w r/w initial value 00000000 123 7753f?avr?01/11 attiny261/attiny461/attiny861 the actual value from the port re gister will be visible on the port pin, when the output compare override enable bit is cleared. table 16-20 shows the output compare override enable bits and their corresponding output compare pins. 16.11.6 tcnt1 ? timer/counter1 this 8-bit register contains the value of timer/counter1. the timer/counter1 is realized as a 10-bit up/ down counter with read and write access. due to synchronization of the cpu, timer/counter1 data written into timer/counter1 is delayed by one and half cpu clock cycles in syn chronous mode and at most o ne cpu clock cycles for asyn- chronous mode. when a 10-bit accuracy is preferred, special procedures must be followed for accessing the 10-bit tcnt1 register via t he 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 112 . alternatively the timer/counter1 can be used as an 8-bit timer/counter. note that the timer/counter1 always starts counting up after writing the tcnt1 register. 16.11.7 tc1h ? timer/counter1 high byte the temporary timer/counter1 register is an 2-bit read/write register. ? bits 7:2 - res: reserved bits these bits are reserved bits in the attiny261/461/861 and always reads as zero. ? bits 1:0 - tc19, tc18: two msb bits of the 10-bit accesses if 10-bit accuracy is used, the timer/counter1 high byte register (tc1h) is used for temporary storing the msb bits (tc19, tc18) of the 10-bi t accesses. the same tc1h register is shared between all 10-bit registers within the timer/counter1. note that special procedures must be fol- lowed when accessing the 10-bit tcnt1 register via the 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 112 . table 16-20. output compare override enable bits vs. output compare pins oc1oe0 oc1oe1 oc1oe2 oc1oe3 oc1oe4 oc1oe5 oc1a (pb0) oc1a (pb1) oc1b (pb2) oc1b (pb3) oc1d (pb4) oc1d (pb5) bit 76543210 0x2e (0x4e) msb lsb tcnt1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x25 (0x45) ------tc19tc18tc1h read/writerrrrrrr/wr/w initial value00000000 124 7753f?avr?01/11 attiny261/attiny461/attiny861 16.11.8 ocr1a ? timer/counter1 output compare register a the output compare register a is an 8-bit read/write register. the timer/counter output compare register a contains data to be continuously compared with timer/counter1. actions on compare matches are specified in tccr1a. a compare match does only occur if timer/counter1 counts to the ocr1a value. a software write that sets tcnt1 and ocr1a to the same value does not generate a compare match. a compare match will set the compar e interrupt flag ocf1a after a synchronization delay follow- ing the compare event. note that, if 10-bit accuracy is used special pr ocedures must be followed when accessing the internal 10-bit output compare registers via the 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 112 . 16.11.9 ocr1b ? timer/counter1 output compare register b the output compare register b is an 8-bit read/write register. the timer/counter output compare register b contains data to be continuously compared with timer/counter1. actions on compare matches are specified in tccr1. a compare match does only occur if timer/counter1 counts to the ocr1b value. a software write that sets tcnt1 and ocr1b to the same value does not generate a compare match. a compare match will set the compar e interrupt flag ocf1b after a synchronization delay follow- ing the compare event. note that, if 10-bit accuracy is used special pr ocedures must be followed when accessing the internal 10-bit output compare registers via the 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 112 . 16.11.10 ocr1c ? timer/counter1 output compare register c the output compare register c is an 8-bit read/write register. the timer/counter output compare register c co ntains data to be continuously compared with timer/counter1, and a compare ma tch will clear tcnt1. this regist er has the same function in normal mode and pwm modes. bit 76543210 0x2d (0x4d) msb lsb ocr1a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x2c (0x4c) msb lsb ocr1b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x2b (0x4b) msb lsb ocr1c read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 125 7753f?avr?01/11 attiny261/attiny461/attiny861 note that, if a smaller value than three is written to the output compare register c, the value is automatically replaced by three as it is a mini mum value allowed to be written to this register. note that, if 10-bit accuracy is used special pr ocedures must be followed when accessing the internal 10-bit output compare registers via the 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 112 . 16.11.11 ocr1d ? timer/counter1 output compare register d the output compare register d is an 8-bit read/write register. the timer/counter output compare register d co ntains data to be continuously compared with timer/counter1. actions on compare matches are specified in tccr1a. a compare match does only occur if timer/counter1 counts to the ocr1d value. a software write that sets tcnt1 and ocr1d to the same value does not generate a compare match. a compare match will set the compar e interrupt flag ocf1d after a synchronization delay follow- ing the compare event. note that, if 10-bit accuracy is used special pr ocedures must be followed when accessing the internal 10-bit output compare registers via the 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 112 . 16.11.12 timsk ? timer/counter1 interrupt mask register ? bit 7- ocie1d: timer/counter1 output compare interrupt enable when the ocie1d bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compare matchd, interrupt is enabled. the corresponding interrupt at vector $010 is executed if a compare matchd occurs. the compare flag in timer/counter1 is set (one) in the timer/counter interrupt flag register. ? bit 6 - ocie1a: timer/counter1 output compare interrupt enable when the ocie1a bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compare matcha, interrupt is enabled. the corresponding interrupt at vector $003 is executed if a compare matcha occurs. the compare flag in timer/counter1 is set (one) in the timer/counter interrupt flag register. ? bit 5 - ocie1b: timer/counter1 output compare interrupt enable when the ocie1b bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compare matchb, interrupt is enabled. the corresponding interrupt at vector $009 is executed if a compare matchb occurs. the compare flag in timer/counter1 is set (one) in the timer/counter interrupt flag register. bit 76543210 0x2a (0x4a) msb lsb ocr1d read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x39 (0x59) ocie1d ocie1a ocie1b ocie0a ocie0b toie1 toie0 ticie0 timsk read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 126 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bit 2 - toie1: timer/counter1 overflow interrupt enable when the toie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt (at vector $004) is executed if an overflow in timer/counter1 occurs . the overflow flag (timer1) is set (one) in the timer/counter interrupt flag register - tifr. 16.11.13 tifr ? timer/counter 1 interrupt flag register ? bit 7- ocf1d: output compare flag 1d the ocf1d bit is set (one) when compare match occurs between timer/counter1 and the data value in ocr1d - output compare register 1d. ocf1d is cleared by hardware when executing the corresponding interrupt handling vector. alte rnatively, ocf1d is cleared, after synchroniza- tion clock cycle, by writing a logic one to the flag. when the i-bit in sreg, ocie1d, and ocf1d are set (one), the timer/counter1 d compare match interrupt is executed. ? bit 6 - ocf1a: output compare flag 1a the ocf1a bit is set (one) when compare match occurs between timer/counter1 and the data value in ocr1a - output compare register 1a. ocf1a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf1a is cleared, after synchroniza- tion clock cycle, by writing a logic one to the flag. when the i-bit in sreg, ocie1a, and ocf1a are set (one), the timer/counter1 a compare match interrupt is executed. ? bit 5 - ocf1b: output compare flag 1b the ocf1b bit is set (one) when compare match occurs between timer/counter1 and the data value in ocr1b - output compare register 1a. ocf1b is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf1b is cleared, after synchroniza- tion clock cycle, by writing a logic one to the flag. when the i-bit in sreg, ocie1b, and ocf1b are set (one), the timer/counter1 b compare match interrupt is executed. ? bit 2 - tov1: timer/counter1 overflow flag in normal mode and fast pwm mode the tov1 bit is set (one) each time the counter reaches top at the same clock cycle when the counter is reset to bottom. in phase and frequency correct pwm mode the tov1 bit is set (one) each time the counter reaches bottom at the same clock cycle when zero is clocked to the counter. the bit tov1 is cleared by hardware when ex ecuting the corresponding interrupt handling vec- tor. alternatively, tov1 is cleared, after sync hronization clock cycle, by writing a logical one to the flag. when the sreg i-bit, and toie1 (tim er/counter1 overflow interrupt enable), and tov1 are set (one), the timer/counter1 overflow interrupt is executed. bit 76543210 0x38 (0x58) ocf1d ocf1a ocf1b ocf0a ocf0b tov1 tov0 icf0 tifr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 127 7753f?avr?01/11 attiny261/attiny461/attiny861 16.11.14 dt1 ? timer/counter1 dead time value the dead time value register is an 8-bit read/write register. the dead time delay of all timer/counter1 channels are adjusted by the dead time value regis- ter, dt1. the register consists of two fields, dt1h3..0 and dt1l3..0, one for each complementary output. therefore a different dead time delay can be adjusted for the rising edge of oc1x and the rising edge of oc1x . ? bits 7:4- dt1h3:dt1h0: dead time value for oc1x output the dead time value for the oc1x output. the dead time delay is set as a number of the pres- caled timer/counter clocks. the minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. ? bits 3:0- dt1l3:dt1l0: dead time value for oc1x output the dead time value for the oc1x output. the dead time delay is set as a number of the pres- caled timer/counter clocks. the minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. bit 76543210 0x24 (0x44) dt1h3 dt1h2 dt1h1 dt1h0 dt1l3 dt1l2 dt1l1 dt1l0 dt1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 128 7753f?avr?01/11 attiny261/attiny461/attiny861 17. usi ? universal serial interface 17.1 features ? two-wire synchronous data tr ansfer (master or slave) ? three-wire synchronous data transfer (master or slave) ? data received interrupt ? wakeup from idle mode ? in two-wire mode: wake-up from all sleep modes, including power-down mode ? two-wire start condition detect or with interr upt capability 17.2 overview the universal serial interface, or usi, provides the basic hardware resources needed for serial communication. combined with a minimum of cont rol software, the usi allows significantly higher transfer rates and uses less code space than solutions based on software only. interrupts are included to minimize the processor load. a simplified block diagram of the usi is shown on figure 17-1. for the actual placement of i/o pins, refer to ?pinout attiny261/461/861? on page 2 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?register descriptions? on page 135 . figure 17-1. universal serial interface, block diagram the 8-bit usi data register is directly accessible via the data bus and contains the incoming and outgoing data. the register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. the usi data register is a serial shift register and the most signif- icant bit that is the output of the serial shi ft register is connected to one of two output pins depending of the wire mode configuration. a transparent latch is inserted between the usi data register output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. the serial input is always sampled from the data input (di) pin independent of the configuration. data bus usipf usitc usiclk usics0 usics1 usioif usioie usidc usisif usiwm0 usiwm1 usisie bit7 two-wire clock control unit do (output only) di/sda (input/open drain) usck/scl (input/open drain) 4-bit counter usidr usisr dq le usicr clock hold tim0 comp bit0 [1] 3 0 1 2 3 0 1 2 0 1 2 usidb 129 7753f?avr?01/11 attiny261/attiny461/attiny861 the 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. both the usi data register and the counter are clocked simultaneously by the same clock source. this allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. note that when an external clock source is selected the counter counts both clock edges. in this case the counter counts the number of edges, and not the number of bits. the clock can be selected from three different sources: the usck pin, timer/counter0 compare match or from software. the two-wire clock control unit can generate an interrupt when a start condition is detected on the two-wire bus. it can also generate wait states by holding the clock pin low after a start con- dition is detected, or after the counter overflows. 17.3 functional descriptions 17.3.1 three-wire mode the usi three-wire mode is compliant to the serial peripheral interface (spi) mode 0 and 1, but does not have the slave select (ss) pin functionality. however, this feature can be implemented in software if necessary. pin names used by this mode are: di, do, and usck. figure 17-2. three-wire mode operat ion, simplified diagram figure 17-2 shows two usi units operating in three-wire mode, one as master and one as slave. the two usi data register are interconnec ted in such way that after eight usck clocks, the data in each register are interchanged. the same clock also increments the usi?s 4-bit coun- ter. the counter overflow (interrupt) flag, or usioif, can therefore be used to determine when a transfer is completed. the clock is generated by the master device software by toggling the usck pin via the port register or by writing a one to the usitc bit in usicr. slave master bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 do di usck bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 do di usck portxn 130 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 17-3. three-wire mode, timing diagram the three-wire mode timing is shown in figure 17 -3. at the top of the figure is a usck cycle ref- erence. one bit is shifted into the usi data register (usidr) for each of these cycles. the usck timing is shown for both external clock mo des. in external clock mode 0 (usics0 = 0), di is sampled at positive edges, and do is changed (data register is shifted by one) at negative edges. external clock mode 1 (usics0 = 1) uses the opposite edges versus mode 0, i.e., sam- ples data at negative and changes the output at positive edges. the usi clock modes corresponds to the spi data mode 0 and 1. referring to the timing diagram (figure 17-3.), a bus transfer involves the following steps: 1. the slave device and master device sets up its data output and, depending on the proto- col used, enables its output driver (mark a and b). the output is set up by writing the data to be transmitted to the usi data register. enabling of the output is done by setting the corresponding bit in the port data direction register. note that point a and b does not have any specific order, but both must be at least one half usck cycle before point c where the data is sampled. this must be done to ensure that the data setup requirement is satisfied. the 4-bit counter is reset to zero. 2. the master generates a clock pulse by software toggling the usck line twice (c and d). the bit value on the slave and master?s data input (di) pin is sampled by the usi on the first edge (c), and the data output is changed on the opposite edge (d). the 4-bit counter will count both edges. 3. step 2. is repeated eight times for a complete register (byte) transfer. 4. after eight clock pulses (i.e., 16 clock edge s) the counter will overfl ow and indicate that the transfer is completed. the data bytes transferred must now be processed before a new transfer can be init iated. the overflow interrupt will wa ke up the processor if it is set to idle mode. depending of the protocol used the slave device can now set its output to high impedance. 17.3.2 spi master operation example the following code demonstrates how to use the usi module as a spi master: spitransfer: sts usidr,r16 ldi r16,(1< 134 7753f?avr?01/11 attiny261/attiny461/attiny861 referring to the timing diagram (figure 17-5.), a bus transfer involves the following steps: 1. the a start condition is generated by the master by forcing the sda low line while the scl line is high (a). sda can be forced low either by writing a zero to bit 7 of the shift register, or by setting the corresponding bit in the port register to zero. note that the usi data register bit must be set to one for the output to be enabled. the slave device?s start detector logic (figure 17-6.) detects the start condition and sets the usisif flag. the flag can generate an interrupt if necessary. 2. in addition, the start detector will hold the scl line low after the master has forced an negative edge on this line (b). this allows the slave to wake up from sleep or complete its other tasks before setting up the usi data register to receive the address. this is done by clearing the start condition flag and reset the counter. 3. the master set the first bit to be transferred and releases the scl line (c). the slave samples the data and shift it into the usi data register at the positive edge of the scl clock. 4. after eight bits are transferred containing slave address and data direction (read or write), the slave counter overflows and the scl line is forced low (d). if the slave is not the one the master has addressed, it releases the scl line and waits for a new start condition. 5. if the slave is addressed it holds the sda line low during the acknowledgment cycle before holding the scl line low again (i.e., the counter register must be set to 14 before releasing scl at (d)). depending of the r/w bit the master or slave enables its output. if the bit is set, a master read operation is in progress (i.e., the slave drives the sda line) the slave can hold the scl line low after the acknowledge (e). 6. multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the master (f). or a new start condition is given. if the slave is not able to receive more data it does not acknowledge the data byte it has last received. when the master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted. figure 17-6. start condition detector, logic diagram 17.3.5 start condition detector the start condition detector is shown in figure 17-6. the sda line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the scl line. the start condition detector is only enabled in two-wire mode. the start condition detector is working asynchronously and can therefore wake up the processor from the power-down sleep mode. however, the protocol used might have restrictions on the scl hold time. therefore, when us ing this feature in this case th e oscillator start-up time set by the cksel fuses (see ?clock systems and their distribution? on page 25 ) must also be taken into the consideration. refer to the usisif bit description on page 136 for further details. sda scl write( usisif) clock hold usisif dq clr dq clr 135 7753f?avr?01/11 attiny261/attiny461/attiny861 17.4 alternative usi usage when the usi unit is not used for serial communi cation, it can be set up to do alternative tasks due to its flexible design. 17.4.1 half-duplex asynchronous data transfer by utilizing the usi data register in three-wire mode, it is possible to implement a more com- pact and higher performance uart than by software only. 17.4.2 4-bit counter the 4-bit counter can be used as a stand-alone counter with overflow interrupt. note that if the counter is clocked externally, both clock edges will generate an increment. 17.4.3 12-bit timer/counter combining the usi 4-bit counter and timer/counter0 allows them to be used as a 12-bit counter. 17.4.4 edge triggered external interrupt by setting the counter to maximum value (f) it can function as an additional external interrupt. the overflow flag and interrupt enable bit are th en used for the external interrupt. this feature is selected by the usics1 bit. 17.4.5 software interrupt the counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. 17.5 register descriptions 17.5.1 usidr ? usi data register when accessing the usi data register (usidr) th e serial register can be accessed directly. if a serial clock occurs at the same cycle the regist er is written, the register will contain the value written and no shift is performed. a (left) shift operation is performed depending of the usics1..0 bits setting. the shift operation c an be controlled by an external clock edge, by a timer/counter0 compare match, or directly by so ftware using the usiclk strobe bit. note that even when no wire mode is selected (usiwm1..0 = 0) both the external data input (di/sda) and the external clock input (usck/scl) can still be used by the usi data register. the output pin in use, do or sda depending on the wire mode, is connected via the output latch to the most significant bit (bit 7) of the data register. the output latch is open (transparent) dur- ing the first half of a serial cloc k cycle when an external clock so urce is selected (usics1 = 1), and constantly open when an internal clock so urce is used (usics1 = 0). the output will be changed immediately when a new msb written as long as the latch is open. the latch ensures that data input is sampled and data output is changed on opposite clock edges. note that the corresponding data direction register to the pin must be set to one for enabling data output from the usi data register. bit 7654 3210 0x0f (0x2f) msb lsb usidr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 136 7753f?avr?01/11 attiny261/attiny461/attiny861 17.5.2 usibr ? usi buffer register the content of the serial register is loaded to the usi buffer register when the transfer is com- pleted, and instead of accessing the usi data register (the serial register) the usi data buffer can be accessed when the cpu reads the receiv ed data. this gives the cpu time to handle other program tasks too as the controlling of the usi is not so timing critical. the usi flags as set same as when reading the usidr register. 17.5.3 usisr ? usi status register the status register contains interrupt flags, line status flags and the counter value. ? bit 7 ? usisif: start condition interrupt flag when two-wire mode is selected, the usisif flag is set (to one) when a start condition is detected. when output disable mode or three-wire mode is selected and (usicsx = 0b11 & usiclk = 0) or (usics = 0b10 & usiclk = 0), any edge on the sck pin sets the flag. an interrupt will be generated when the flag is set while th e usisie bit in usicr and the global interrupt enable flag are set. the flag will only be cleared by writing a logical one to the usisif bit. clearing this bit will release the start de tection hold of uscl in two-wire mode. a start condition interr upt will wakeup the processor from all sleep modes. ? bit 6 ? usioif: counter overflow interrupt flag this flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). an interrupt will be generate d when the flag is set while the usioie bit in usicr and the global interrupt enable flag ar e set. the flag will only be cleared if a one is written to the usioif bit. clearing this bit will release the counter overfl ow hold of scl in two-wire mode. a counter overflow interrupt will wake up the processor from idle sleep mode. ? bit 5 ? usipf: stop condition flag when two-wire mode is selected, the usipf flag is set (one) when a stop condition is detected. the flag is cleared by writing a one to this bit. note that this is not an interrupt flag. this signal is useful when implementing two-wire bus master arbitration. ? bit 4 ? usidc: data output collision this bit is logical one when bit 7 in the usi data register differs from the physical pin value. the flag is only valid when two-wire mode is used. this signal is useful when implementing two-wire bus master arbitration. ? bits 3:0 ? usicnt3..0: counter value these bits reflect the current 4-bit counter value. the 4-bit counter value can directly be read or written by the cpu. bit 7 6 5 4 3 2 1 0 0x10 (0x30) msb lsb usibr read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7654 3 2 1 0 0x0e (0x2e) usisif usioif usipf usidc usic nt3 usicnt2 usicnt1 usicnt0 usisr read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 137 7753f?avr?01/11 attiny261/attiny461/attiny861 the 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a timer/counter0 compare match, or by software using usiclk or usitc strobe bits. the clock source depends of the setting of the usics1..0 bits. for external clock operation a special feature is added that allows the clock to be generated by writing to the usitc strobe bit. this feature is enabled by write a one to the usiclk bit while setting an external clock source (usics1 = 1). note that even when no wire mode is selected (usiwm1..0 = 0) the external clock input (usck/scl) are can still be used by the counter. 17.5.4 usicr ? usi control register the control register includes interrupt enable control, wire mode setting, clock select setting, and clock strobe. ? bit 7 ? usisie: start condition interrupt enable setting this bit to one enables the start condition detector interrupt. if there is a pending inter- rupt when the usisie and the globa l interrupt enable flag is set to one, this will immediately be executed. refer to the usisif bit description on page 136 for further details. ? bit 6 ? usioie: counter overflow interrupt enable setting this bit to one enables the counter overflow interrupt. if there is a pending interrupt when the usioie and the global interrupt enable flag is set to one, this will immediately be executed. refer to the usioif bit description on page 136 for further details. ? bit 5:4 ? usiwm1:0: wire mode these bits set the type of wire mode to be us ed. basically only the function of the outputs are affected by these bits. data and clock inputs are not affected by the mode selected and will always have the same function. the counter and usi data register can therefore be clocked externally, and data input sampled, even when outputs are disabled. the relations between usiwm1:0 and the usi operation is summarized in table 17-1 . bit 7 6 5 4 3 2 1 0 0x0d (0x2d) usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc usicr read/write r/w r/w r/w r/w r/w r/w w w initial value 0 0 0 0 0 0 0 0 138 7753f?avr?01/11 attiny261/attiny461/attiny861 note: 1. the di and usck pins are renamed to serial data (sda) and serial clock (scl) respectively to avoid confusion between the modes of operation. ? bit 3:2 ? usics1:0: clock source select these bits set the clock source for the usi da ta register and counter. the data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (di/sda) when using external clock source (usck/scl). when software strobe or timer/counter0 compare match clock option is selected, the output latch is transparent and therefore the output is changed immediately. clearing the usics1:0 bits enables software strobe option. when using this option, writing a one to the usiclk bit clocks both the usi data register and the counter. for external clock sour ce (usics1 = 1), the usiclk bit is no longer used as a strobe, but selects between external clocking and software clocking by the usitc strobe bit. table 17-2 on page 139 shows the relationship between the usics1..0 and usiclk setting and clock source used for the usi data register and the 4-bit counter. table 17-1. relations between usiwm1..0 and the usi operation usiwm1 usiwm0 description 0 0 outputs, clock hold, and start detector disabled. port pins operates as normal. 01 three-wire mode. uses do, di, and usck pins. the data output (do) pin overrides the corresponding bit in the port register in this mode. however, the corresponding ddr bit still controls the data direction. when the port pin is set as input the pins pull-up is controlled by the port bit. the data input (di) and serial clock (usck) pins do not affect the normal port operation. when operating as master, clock pulses are software generated by toggling the port register, while the data direction is set to output. the usitc bit in the usicr register can be used for this purpose. 10 two-wire mode. uses sda (di) and scl (usck) pins (1) . the serial data (sda) and the serial clock (scl) pins are bi-directional and uses open-collector output drives. the output drivers are enabled by setting the corresponding bit for sda and scl in the ddr register. when the output driver is enabled for the sd a pin, the output driver will force the line sda low if the output of the usi data register or the corresponding bit in the port register is zero. otherwise the sda line will not be driven (i.e., it is released). when the scl pin output driver is enabled the scl line will be forced low if the corresponding bit in the port re gister is zero, or by the start detector. otherwise the scl line will not be driven. the scl line is held low when a start detector detects a start condition and the output is enabled. clearing the start condition flag (usisif) releases the line. the sda and scl pin inputs is not affected by enabling this mode. pull-ups on the sda and scl port pin are disabled in two-wire mode. 11 two-wire mode. uses sda and scl pins. same operation as for the two-wire mode described above, except that the scl line is also held low when a counter overflow occurs, and is held low until the counter overflow flag (usioif) is cleared. 139 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bit 1 ? usiclk: clock strobe writing a one to this bit location strobes the usi data register to shift one step and the counter to increment by one, provided that the usics1..0 bits are set to zero and by doing so the soft- ware clock strobe option is selected. the output will change immediately when the clock strobe is executed, i.e., in the same instruction cycle. the value shifted into the usi data register is sampled the previous in struction cycle. the bit will be read as zero. when an external clock source is selected (usics1 = 1), the usiclk function is changed from a clock strobe to a clock select register. setting the usiclk bit in this case will select the usitc strobe bit as clock sour ce for the 4-bit counter (see table 17-2 ). ? bit 0 ? usitc: toggle clock port pin writing a one to this bit location toggles the usck/s cl value either from 0 to 1, or from 1 to 0. the toggling is independent of the setting in the data direction register, but if the port value is to be shown on the pin the ddb2 must be set as output (to one). this feature allows easy clock generation when implementi ng master devices. the bit will be read as zero. when an external clock source is selected (usics 1 = 1) and the usiclk bit is set to one, writ- ing to the usitc strobe bit will directly clock th e 4-bit counter. this allows an early detection of when the transfer is done when operating as a master device. 17.5.5 usipp ? usi pin position ? bits 7:1 ? res: reserved bits these bits are reserved bits in the attiny261/461/861 and always reads as zero. ? bit 0 ? usipos: usi pin position setting this bit to one changes the usi pin position. as default pins pb2..pb0 are used for the usi pin functions, but when writing this bit to one the usipos bit is set the usi pin functions are on pins pa2..pa0. table 17-2. relations between the usics1..0 and usiclk setting usics1 usics0 usiclk usi data register clock source 4-bit counter clock source 0 0 0 no clock no clock 001 software clock strobe (usiclk) software clock strobe (usiclk) 01x timer/counter0 compare match timer/counter0 compare match 1 0 0 external, positive edge external, both edges 1 1 0 external, negative edge external, both edges 1 0 1 external, positive edge software clock strobe (usitc) 1 1 1 external, negative edge software clock strobe (usitc) bit 76543210 0x11 (0x31) -------usiposusipp read/writerrrrrrrr/w initial value00000000 140 7753f?avr?01/11 attiny261/attiny461/attiny861 18. ac ? analog comparator the analog comparator compares the input values on the selectable positive pin (ain0, ain1 or ain2) and selectable negative pin (ain0, ain1 or ain2). when the voltage on the positive pin is higher than the voltage on the negative pin, the analog comparator output, aco, is set. the comparator can trigger a separate interrupt, excl usive to the analog comparator. the user can select interrupt triggering on comparator output ri se, fall or toggle. a block diagram of the com- parator and its surrounding logic is shown in figure 18-1 . figure 18-1. analog comparator block diagram (2) notes: 1. see table 18-2 on page 142 . 2. refer to figure 1-1 on page 2 and table 12.3.2 on page 66 for analog comparator pin placement. 18.1 register description 18.1.1 acsra ? analog comparator control and status register a ? bit 7 ? acd: analog comparator disable when this bit is written logic one , the power to the analog comparator is switched off. this bit can be set at any time to tu rn off the analog com parator. this will reduce power consumption in active and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsra. otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set an internal 1.1v referenc e voltage replaces the positive input to the analog comparator. the selection of the internal volta ge reference is done by writing the refs2..0 bits in admux register. when this bi t is cleared, ain0, ain1 or ain2 depending on the acm2..0 bits is applied to the positive input of the analog comparator. acbg bandgap reference adc multiplexer output acme aden (1) mux ain0 ain1 ain2 acm2..1 hsel hlev bit 76543210 0x08 (0x28) acd acbg aco aci acie acme acis1 acis0 acsra read/write r/w r/w r r/w r/w r/w r/w r/w initial value00n/a00000 141 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bit 5 ? aco: analog comparator output the output of the analog comparator is synchronized and then directly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interr upt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when executing the corresponding inter- rupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i-bi t in the status register is set, the analog com- parator interrupt is activated. when written logic zero, the interrupt is disabled. ? bit 2 ? acme: analog comparator multiplexer enable when this bit is written logic one and the adc is switched off (aden in adcsra is zero), the adc multiplexer selects the negative input to the analog comparator. when this bit is written logic zero, ain1 is applied to the negative input of the analog comparator. for a detailed description of this bit, see ?analog comparator multiplexed input? on page 142 . ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator interrupt. the different settings are shown in table 18-1 . when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. 18.2 analog comparator multiplexed input when the analog to digital converter (adc) is configured as single ended input channel, it is possible to select any of the adc10..0 pins to replace the negative input to the analog compar- ator. the adc multiplexer is used to select this input, and consequently, the adc must be switched off to utilize this feature. if the analog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is switched off (a den in adcsra is zero), mux5..0 in admux select the input pin to replace the negative input to the analog comparator, as shown in table 18-2 . if acme is cleared or aden is set, either ain0, ain1 or ain2 is applied to the negative input to the analog comparator. table 18-1. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. 142 7753f?avr?01/11 attiny261/attiny461/attiny861 table 18-2. analog comparator multiplexed input acme aden mux5..0 acm2..0 posi tive input neg ative input 0 x xxxxxx 000 ain0 ain1 0 x xxxxxx 001 ain0 ain2 0 x xxxxxx 010 ain1 ain0 0 x xxxxxx 011 ain1 ain2 0 x xxxxxx 100 ain2 ain0 0 x xxxxxx 101,110,111 ain2 ain1 1 1 xxxxxx 000 ain0 ain1 1 0 000000 000 ain0 adc0 1 0 000000 01x ain1 adc0 1 0 000000 1xx ain2 adc0 1 0 000001 000 ain0 adc1 1 0 000001 01x ain1 adc1 1 0 000001 1xx ain2 adc1 1 0 000010 000 ain0 adc2 1 0 000010 01x ain1 adc2 1 0 000010 1xx ain2 adc2 1 0 000011 000 ain0 adc3 1 0 000011 01x ain1 adc3 1 0 000011 1xx ain2 adc3 1 0 000100 000 ain0 adc4 1 0 000100 01x ain1 adc4 1 0 000100 1xx ain2 adc4 1 0 000101 000 ain0 adc5 1 0 000101 01x ain1 adc5 1 0 000101 1xx ain2 adc5 1 0 000110 000 ain0 adc6 1 0 000110 01x ain1 adc6 1 0 000110 1xx ain2 adc6 1 0 000111 000 ain0 adc7 1 0 000111 01x ain1 adc7 1 0 000111 1xx ain2 adc7 1 0 001000 000 ain0 adc8 1 0 001000 01x ain1 adc8 1 0 001000 1xx ain2 adc8 1 0 001001 000 ain0 adc9 1 0 001001 01x ain1 adc9 1 0 001001 1xx ain2 adc9 1 0 001010 000 ain0 adc10 1 0 001010 01x ain1 adc10 1 0 001010 1xx ain2 adc10 143 7753f?avr?01/11 attiny261/attiny461/attiny861 18.2.1 acsrb ? analog comparator control and status register b ? bit 7 ? hsel: hysteresis select when this bit is written logic one, the hysteresis of the analog comparator is switched on. the hysteresis level is se lected by the hlev bit. ? bit 6 ? hlev: hysteresis level when the hysteresis is enabled by the hsel bit, the hysteresis level, hlev, bit selects the hys- teresis level that is either 20mv (hlev=0) or 50mv (hlev=1). ? bit 2:0 ? acm2:acm0: analog comparator multiplexer the analog comparator multiplexer bits select th e positive and negative input pins of the analog comparator. the different settings are shown in table 18-2 . bit 76543210 0x09 (0x29) hsel hlev - - - acm2 acm1 acm0 acsrb read/write r/w r/w r r r r/w r/w r/w initial value00n/a00000 144 7753f?avr?01/11 attiny261/attiny461/attiny861 19. adc ? analog to digital converter 19.1 features ? 10-bit resolution ? 1.0 lsb integral non-linearity ? 2 lsb absolute accuracy ? 65 - 260 s conversion time ? up to 15 ksps at maximum resolution ? 11 multiplexed single ended input channels ? 16 differential input pairs ? 15 differential input pa irs with selectable gain ? temperature sensor input channel ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 1.1v / 2.56v adc voltage reference ? free running or single conversion mode ? adc start conversion by auto tr iggering on interrupt sources ? interrupt on adc conversion complete ? sleep mode noise cancel ? unipolar/ bipolar input mode ? input polarity reversal mode 19.2 overview the attiny261/461/861 features a 10-bit successive approximation adc. the adc is connected to a 11-channel analog multiplexer which allows 16 differential voltage input combinations and 11 single-ended voltage inputs constructed from the pins pa7..pa0 or pb7..pb4. the differential input is equipped with a programmable gain stage, providing amplification steps of 1x, 8x, 20x or 32x on the differential input voltage before the a/d conversion. the single-ended voltage inputs refer to 0v (gnd). the adc contains a sample and hold circuit whic h ensures that the input voltage to the adc is held at a constant level during conversion . a block diagram of the adc is shown in figure 19-1 . internal reference voltages of nominally 1.1v or 2.56v are provided on-chip. the internal refer- ence voltage of 2.56v, can optionally be externa lly decoupled at the aref (pa3) pin by a capacitor, for better noise performance. alternatively, v cc can be used as reference voltage for single ended channels. there is also an option to use an external voltage reference and turn-off the internal voltage reference. these options are selected using the refs2:0 bits of the admux control register. 145 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 19-1. analog to digital converter block schematic 19.3 operation the adc converts an analog input voltage to a 10-bit digital value through successive approxi- mation. the minimum value represents gnd and the maximum value represents the voltage on v cc , the voltage on the aref pin or an internal 1.1v / 2.56v voltage reference. the voltage reference for the adc may be selected by writing to the refs2..0 bits in admux. the vcc supply, the aref pin or an internal 1.1v / 2.56v voltage reference may be selected as the adc voltage reference. optionally the internal 1.1v / 2.56v voltage reference may be decou- pled by an external capacitor at the aref pin to improve noise immunity. the analog input channel and differential gain are selected by writing to the mux5..0 bits in admux. any of the 11 adc input pins adc10..0 ca n be selected as single ended inputs to the adc. the positive and negative inputs to the differential gain amplifier are described in table 19-5 . if differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input pair by the selected gain factor, 1x, 8x, 20x or 32x, according to the setting of the mux5..0 bits in admux and the gs el bit in adcsrb. this amplified value then becomes the analog input to the adc. if single ended channels are used, the gain amplifier is bypassed altogether. adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl. & status register a (adcsra) adc data register (adch/adcl) mux2 adie adate adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux3 conversion logic 10-bit dac + - sample & hold comparator mux decoder mux4 adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 refs0 refs1 adlar + - channel selection gain selection adc[9:0] adc multiplexer output gain amplifier internal 1.18v reference prescaler single ended / differential selection agnd pos. input mux neg. input mux adc10 adc9 adc8 vcc aref temperature sensor internal 2.56/1.1v reference mux adc ctrl. & status register b (adcsrb) refs2 gsel mux5 146 7753f?avr?01/11 attiny261/attiny461/attiny861 if the same adc input pin is selected as both the positive and negative input to the differential gain amplifier, the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion. this figure can be subtracted from subsequent conver- sions with the same gain setting to reduce offset error to below 1 lsw. the on-chip temperature sensor is selected by writing the code ?111111? to the mux5..0 bits in admux register when the adc11 chan nel is used as an adc input. the adc is enabled by setting the adc enable bit, aden in adcsra. voltage reference and input channel selections will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is pr esented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been r ead, and a conversion completes before adch is read, neither register is updated and the result fr om the conversion is lost. when adch is read, adc access to the adch and ad cl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. when adc access to the data registers is prohibited between r eading of adch and ad cl, the in terrupt will trigger even if the result is lost. 19.4 starting a conversion a single conversion is started by writing a l ogical one to the adc start conversion bit, adsc. this bit stays high as long as the conversi on is in progress and will be cleared by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current conv ersion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bi t, adate in adcsra. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is st arted. this provides a method of starting con- versions at fixed intervals. if the trigger signal still is set when the conversion completes, a new conversion will not be star ted. if another positive edge occurs on the trigger si gnal during con- version, the edge will be ignored. note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 147 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 19-2. adc auto trigger logic using the adc interrupt flag as a trigger source makes the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, con- stantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcs ra. in this mode the adc will perform successive conversions independently of whether the a dc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conversi ons can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit will be read as one during a conversion, independently of how the conversion was started. 19.5 prescaling and conversion timing figure 19-3. adc prescaler by default, the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz to get maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 200 khz to get a higher sample rate. the adc module contains a prescaler, which generates an acceptable adc clock frequency from any cpu frequency above 100 khz. the presca ling is set by the adps bits in adcsra. adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start 148 7753f?avr?01/11 attiny261/attiny461/attiny861 the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as lo ng as the aden bit is set, and is continuously reset when aden is low. when initiating a single ended conversion by se tting the adsc bit in adcsra, the conversion starts at the following rising edge of the adc clock cycle. a normal conversion takes 13 adc clock cycles. the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conver- sion and 14.5 adc clock cycles after the start of an first conv ersion. when a conversion is complete, the result is written to the adc data re gisters, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be init iated on the first rising adc clock edge. when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clock cycles after the rising edge on the trigger source signal. three addi- tional cpu clock cycles are used for synchronization logic. in free running mode, a new conversion will be started immediately after the conversion com- pletes, while adsc remains high. for a summary of conversion times, see table 19-1 . figure 19-4. adc timing diagram, first conver sion (single conversion mode) figure 19-5. adc timing diagram, single conversion sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and refs update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 149 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 19-6. adc timing diagram, auto triggered conversion figure 19-7. adc timing diagram, free running conversion 19.6 changing channel or reference selection the mux5:0 and refs2:0 bits in the admux register are single buffered through a temporary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point dur ing the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. con- tinuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). table 19-1. adc conversion time condition sample & hold (cycles from start of conversion ) total conversion time (cycles) first conversion 13.5 25 normal conversions 1.5 13 auto triggered conversions 2 13.5 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock trigger source adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset sample & hold mux and refs update 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 150 7753f?avr?01/11 attiny261/attiny461/attiny861 note that the conversion starts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of t he triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settings. if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: a. when adate or aden is cleared. b. during conversion, minimum one adc clock cycle after the trigger event. c. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. 19.6.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: in single conversion mode, always select the channel before starting the conversion. the chan- nel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. in free running mode, always select the channel before starting the first conversion. the chan- nel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. since the next conver sion has already started automati cally, the next result will reflect the previous channel selection. subsequent conversions will refl ect the new channel selection. 19.6.2 adc voltage reference the voltage reference for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in code s close to 0x3ff. v ref can be selected as either v cc , or internal 1.1v / 2.56v voltage reference, or external aref pin. the first adc con- version result after switching voltage reference source may be inaccurate, and the user is advised to discard this result. 151 7753f?avr?01/11 attiny261/attiny461/attiny861 19.7 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: a. make sure that the adc is enabled and is not busy converting. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. b. enter adc noise reduction mode (or idle mode). the adc will start a conversion once the cpu has been halted. c. if no other interrupts occur before the adc conversion completes, the adc interrupt will wake up the cpu and execute the adc co nversion complete in terrupt routine. if another interrupt wakes up the cpu before the adc conversion is complete, that interrupt will be executed, and an adc conv ersion complete inte rrupt request will be generated when the adc conversion complete s. the cpu will remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before enter- ing such sleep modes to avoid excessive power consumption. 19.7.1 analog input circuitry the analog input circuitry for single ended channels is illustrated in figure 19-8. an analog source applied to adcn is subjected to the pin capacitance and input leakage of that pin, regard- less of whether that channel is selected as input for the adc. when the channel is selected, the source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals with an output impedance of approximately 10 k or less. if such a source is used, the sampling time will be negligible. if a source with higher imped- ance is used, the sampling time will depend on how long time the source nee ds to charge the s/h capacitor, with can vary widely. the user is recommended to only use low impedent sources with slowly varying signals, since this minimizes the required charge transfer to the s/h capacitor. signal components higher than the nyquist frequency (f adc /2) should not be present to avoid distortion from unpredictable signal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. figure 19-8. analog input circuitry adcn i ih 1..100 k c s/h = 14 pf v cc /2 i il 152 7753f?avr?01/11 attiny261/attiny461/attiny861 19.7.2 analog noise canceling techniques digital circuitry inside and outside the device ge nerates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b. use the adc noise canceler function to reduce induced noise from the cpu. c. if any port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. 19.7.3 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 19-9. offset error ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb output code v ref input voltage ideal adc actual adc offset error 153 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 19-10. gain error ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. figure 19-11. integral non-linearity (inl) ? differential non-linearity (dnl): the maximum de viation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. output code v ref input voltage ideal adc actual adc gain error output code v ref input voltage ideal adc actual adc inl 154 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 19-12. differential non-linearity (dnl) ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) will c ode to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. 19.8 adc conversion result after the conversion is complete (adif is high ), the conversion result can be found in the adc result registers (adcl, adch). the form of the conversion result depends on the type of the conversion as there are three types of conv ersions: single ended conversion, unipolar differen- tial conversion and bipolar differential conversion. 19.8.1 single ended conversion for single ended conversion, the result is where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 19-4 on page 157 and table 19-5 on page 158 ). 0x000 represents analog ground, and 0x3ff represents the selected voltage reference minus one lsb. the result is presented in one-sided form, from 0x3ff to 0x000. 19.8.2 unipolar differential conversion if differential channels and an unipolar input mode are used, the result is where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, and v ref the selected voltage reference (see table 19-4 on page 157 and table 19-5 on page 158 ). the voltage on the positive pin must always be larger than the voltage on the negative pin or otherwise the voltage difference is saturated to zero. the result is presented in one-sided form, from 0x000 (0d) to 0x3ff (+1023d). the gain is either 1x, 8x, 20x or 32x. output code 0x3ff 0x000 0 v ref input voltage dnl 1 lsb adc v in 1024 ? v ref ----------------------------- = adc v pos v neg ? () 1024 ? v ref ---------------------------------------------------------- - gain ? = 155 7753f?avr?01/11 attiny261/attiny461/attiny861 19.8.3 bipolar differential conversion as default the adc converter operates in the unipolar input mode, but the bipolar input mode can be selected by writing the bin bit in the adcsrb to one. in the bipolar input mode two-sided voltage differences are allowed and thus the voltage on the negative input pin can also be larger than the voltage on the positive input pin. if di fferential channels and a bipolar input mode are used, the result is where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, and v ref the selected voltage reference. the result is presented in two?s complement form, from 0x200 (-512d) through 0x000 (+0d) to 0x1ff (+511d). the gain is either 1x, 8x, 20x or 32x. however, if the signal is not bipolar by nature (9 bits + sign as the 10th bit), this scheme loses one bit of the converter dynamic range. then, if the user wants to perform the conversion with the maximum dynamic range, the user can perfor m a quick polarity check of the result and use the unipolar differential conversion with selectabl e differential input pair. when the polarity check is performed, it is sufficient to read the msb of the result (adc9 in adch). if the bit is one, the result is negative, and if this bi t is zero, the result is positive. 19.9 temperature measurement the temperature measurement is based on an on-ch ip temperature sensor that is coupled to a single ended adc input. mux[4..0] bits in admux register enables the temperature sensor. the internal 1.1v voltage reference must also be selected for the adc voltage reference source in the temperature sensor measurement. when the temperature sensor is enabled, the adc con- verter can be used in single conversion mode to measure the voltage over the temperature sensor. the measured voltage has a linear relationship to the temperature as described in table 19-2 . the voltage sensitivity is approximately 1lsb/ c and the accuracy of the temperature measure- ment is 10 c using manufacturing calibration values (ts_gain, ts_offset). the values described in table 19-2 are typical values. however, due to the process variation the temperature sensor output varies from one chip to another. adc v pos v neg ? () 512 ? v ref ------------------------------------------------------- gain ? = table 19-2. temperature vs. sensor output voltage (typical case): example adc values temperature / c -40c +25 c +125 c 0x00f6 0x0144 0c01b8 156 7753f?avr?01/11 attiny261/attiny461/attiny861 19.9.1 manufacturing calibration calibration values determined during test are available in the signature row. the temperature in degrees celsius can be calculated using the formula: where: a. adch & adcl are the adc data registers, b. is the temperature sensor gain c. ts_offset is the temperature sensor offset correction term ts_gain is the unsigned fixed point 8-bit temperature sensor gain factor in 1/128th units stored in the signature row. ts_offset is the signed twos complement temperature sensor offset reading stored in the sig- nature row. the table below summarizes the parameter signature row address vs product. the following code example allows to read signature row data .equ ts_gain = 0x0007 .equ ts_offset = 0x0005 ldi r30,low(ts_gain) ldi r31,high (ts_gain) rcall read_signature_row mov r17,r16 ; save r16 result ldi r30,low(ts_offset) ldi r31,high (ts_offset) rcall read_signature_row ; r16 holds ts_offset and r17 holds ts_gain read_signature_row: in r16,spmcsr ; wait for spmen ready sbrc r16,spmen ; exit loop here when spmcsr is free rjmp read_signature_row ldi r16,((1< 158 7753f?avr?01/11 attiny261/attiny461/attiny861 table 19-5. input channel selections mux5..0 single ended input positive differential input negative differential input gain 000000 adc0 (pa0) na na na 000001 adc1 (pa1) 000010 adc2 (pa2) 000011 adc3 (pa4) 000100 adc4 (pa5) 000101 adc5 (pa6) 000110 adc6 (pa7) 000111 adc7 (pb4) 001000 adc8 (pb5) 001001 adc9 (pb6) 001010 adc10 (pb7) 001011 na adc0 (pa0) adc1 (pa1) 20x 001100 adc0 (pa0) adc1 (pa1) 1x 001101 adc1 (pa1) adc1 (pa1) 20x 001110 adc2 (pa2) adc1 (pa1) 20x 001111 adc2 (pa2) adc1 (pa1) 1x 010000 n/a adc2 (pa2) adc3 (pa4) 1x 010001 adc3 (pa4) adc3 (pa4) 20x 010010 adc4 (pa5) adc3 (pa4) 20x 010011 adc4 (pa5) adc3 (pa4) 1x 010100 na adc4 (pa5) adc5 (pa6) 20x 010101 adc4 (pa5) adc5 (pa6) 1x 010110 adc5 (pa6) adc5 (pa6) 20x 010111 adc6 (pa7) adc5 (pa6) 20x 011000 adc6 (pa7) adc5 (pa6) 1x 011001 na adc8 (pb5) adc9 (pb6) 20x 011010 adc8 (pb5) adc9 (pb6) 1x 011011 adc9 (pb6) adc9 (pb6) 20x 011100 adc10 (pb7) adc9 (pb6) 20x 011101 adc10 (pb7) adc9 (pb6) 1x 011110 1.1v n/a n/a n/a 011111 0v 159 7753f?avr?01/11 attiny261/attiny461/attiny861 100000 n/a adc0(pa0) adc1(pa1) 20x/32x 100001 adc0(pa0) adc1(pa1) 1x/8x 100010 adc1(pa1 adc0(pa0) 20x/32x 100011 adc1(pa1) adc0(pa0) 1x/8x 100100 n/a adc1(pa1) adc2(pa2) 20x/32x 100101 adc1(pa1) adc2(pa2) 1x/8x 100110 adc2(pa2 adc1(pa1) 20x/32x 100111 adc2(pa2) adc1(pa1) 1x/8x 101000 n/a adc2(pa2) adc0(pa0) 20x/32x 101001 adc2(pa2) adc0(pa0) 1x/8x 101010 adc0(pa0) adc2(pa2) 20x/32x 101011 adc0(pa0) adc2(pa2) 1x/8x 101100 n/a adc4(pa5) adc5(pa6) 20x/32x 101101 adc4(pa5) adc5(pa6) 1x/8x 101110 adc5(pa6) adc4(pa5) 20x/32x 101111 adc5(pa6) adc4(pa5) 1x/8x 110000 n/a adc5(pa6) adc6(pa7) 20x/32x 110001 adc5(pa6) adc6(pa7) 1x/8x 110010 adc6(pa7) adc5(pa6) 20x/32x 110011 adc6(pa7) adc5(pa6) 1x/8x 110100 n/a adc6(pa7) adc4(pa5) 20x/32x 110101 adc6(pa7) adc4(pa5) 1x/8x 110110 adc4(pa5) adc6(pa7) 20x/32x 110111 adc4(pa5) adc6(pa7) 1x/8x 111000 n/a adc0(pa0) adc0(pa0) 20x/32x 111001 adc0(pa0) adc0(pa0) 1x/8x 111010 adc1(pa1) adc1(pa1) 20x/32x 111011 adc2(pa2) adc2(pa2) 20x/32x 111100 n/a adc4(pa5) adc4(pa5) 20x/32x 111101 adc5(pa6) adc5(pa6) 20x/32x 111110 adc6(pa7) adc6(pa7) 20x/32x 111111 adc11 (1) n/a n/a n/a 1. for temperature sensor table 19-5. input channel selections (continued) mux5..0 single ended input positive differential input negative differential input gain 160 7753f?avr?01/11 attiny261/attiny461/attiny861 19.10.2 adcsra ? adc control and status register a ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by writi ng it to zero, the adc is turned off. turning the adc off while a conversion is in prog ress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the first conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will take 25 adc clock cycles instead of the norma l 13. this first conversi on performs initializa- tion of the adc. adsc will read as one as long as a conversion is in progress. when the co nversion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to on e, auto triggering of the adc is enabled. the adc will start a con- version on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if th e adie bit and the i-bit in sreg are set. adif is cleared by hardware when executing the corres ponding interrupt handling vector. alternatively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify-write on adcsra, a pending interrupt can be disabled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sreg is set, the adc conversion complete inter- rupt is activated. ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor betwee n the system clock frequency and the input clock to the adc. bit 76543210 0x06 (0x26) aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 161 7753f?avr?01/11 attiny261/attiny461/attiny861 19.10.3 adcl and adch ? the adc data register 19.10.3.1 adlar = 0 19.10.3.2 adlar = 1 when an adc conversion is complete, the result is found in these two registers. when adcl is read, the adc data register is not updated unt il adch is read. consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adla r is cleared (default), the result is right adjusted. ? adc9:0: adc conversion result these bits represent the result from the conversion, as detailed in ?adc conversion result? on page 154 . table 19-6. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 bit 151413121110 9 8 0x05 (0x25) ??????adc9adc8adch 0x04 (0x24) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/write rrrrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 0x05 (0x25) adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch 0x04 (0x24) adc1 adc0 ??????adcl 76543210 read/write rrrrrrrr rrrrrrrr initial value00000000 00000000 162 7753f?avr?01/11 attiny261/attiny461/attiny861 19.10.4 adcsrb ? adc control and status register b ? bit 7? bin: bipolar input mode the gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the bin bit in the adcsrb register. in the unipolar mode only one-sided conversions are supported and the voltage on the positive input must always be larger than the voltage on the negative input. otherwise the result is saturated to the voltage reference. in the bipolar mode two-sided conversions are supported and the result is represented in the two?s complement form. in the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit. ? bits 6 ? gsel: gain select the gain select bit selects the 32x gain instead of the 20x gain and the 8x gain instead of the 1x gain when the gain select bit is written to one. ? bits 5 ? res: reserved bit this bit is a reserved bit in the attiny 261/461/861 and will always read as zero. ? bits 4 ? refs2: reference selection bit these bit selects either the voltage reference of 1.1 v or 2.56 v for the adc, as shown in table 19-4 . if active channels are used, using avcc or an external aref higher than (avcc - 1v) is not recommended, as this will affect adc accuracy. the inter nal voltage reference options may not be used if an external voltage is being applied to the aref pin. ? bits 3 ? mux5: analog channel and gain selection bit 5 the mux5 bit is the msb of the analog channel and gain selection bits. refer to table 19-5 for details. if this bit is changed during a conver sion, the change will not go into effect until this conversion is complete (adif in adcsra is set). ? bits 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to one, the value of these bits selects which source will trigger an adc conversion. if adate is cleared, the adts2:0 settings will have no effect. a conversion will be triggered by the risi ng edge of the selected interrupt flag . note that switch ing from a trig- ger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. if aden in adcsra is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not cause a trigger event, even if t he adc interrupt flag is set. bit 7 6543210 0x03 (0x23) bin gsel - refs2 mux5 adts2 adts1 adts0 adcsrb read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 163 7753f?avr?01/11 attiny261/attiny461/attiny861 19.10.5 didr0 ? digital input disable register 0 ? bits 7:4,2:0 ? adc6d:adc0d: adc6:0 digital input disable when this bit is written logic one, the digita l input buffer on the corresponding adc pin is dis- abled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc7:0 pin and the di gital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ? bit 3 ? arefd: aref digital input disable when this bit is written logic on e, the digital input buffer on the aref pin is disabled. the corre- sponding pin register bit will alwa ys read as zero when this bit is set. when an analog signal is applied to the aref pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 19.10.6 didr1 ? digital input disable register 1 ? bits 7..4 ? adc10d..adc7d: adc10..7 digital input disable when this bit is written logic one, the digita l input buffer on the corresponding adc pin is dis- abled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc10:7 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. table 19-7. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match a 1 0 0 timer/counter0 overflow 1 0 1 timer/counter0 compare match b 1 1 0 timer/counter1 overflow 1 1 1 watchdog interrupt request bit 76543210 0x01 (0x21) adc6d adc5d adc4d adc3d arefd adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x02 (0x22) adc10d adc9d adc8d adc7d - didr1 read/write r/w r/w r/w r/w r r r r initial value 0 0 0 0 0 0 0 0 164 7753f?avr?01/11 attiny261/attiny461/attiny861 20. debugwire on-chip debug system 20.1 features ? complete program flow control ? emulates all on-chip func tions, both digital and analog, except reset pin ? real-time operation ? symbolic debugging support (both at c and assembler source level, or for other hlls) ? unlimited number of prog ram break points (using software break points) ? non-intrusive operation ? electrical characteristics identical to real device ? automatic configuration system ? high-speed operation ? programming of non-volatile memories 20.2 overview the debugwire on-chip debug system uses a one-wire, bi-directional interface to control the program flow, execute avr instructions in the cpu and to program the different non-volatile memories. 20.3 physical interface when the debugwire enable (dwen) fuse is programmed and lock bits are unprogrammed, the debugwire system within the target device is activated. the reset port pin is configured as a wire-and (open-drain) bi-directional i/o pin with pull-up enabled and becomes the commu- nication gateway between target and emulator. figure 20-1. the debugwire setup figure 20-1 shows the schematic of a target mcu, with debugwire enabled, and the emulator connector. the system clock is not affected by debugwire and will always be the clock source selected by the cksel fuses. dw gnd dw(reset) vcc 1.8 - 5.5v 165 7753f?avr?01/11 attiny261/attiny461/attiny861 when designing a system where debugwire will be used, the following observations must be made for correct operation: ? pull-up resistor on the dw/(reset) line must be in the ra nge of 10k to 20 k . however, the pull-up resistor is optional. ? connecting the reset pin directly to v cc will not work. ? capacitors inserted on the reset pin must be disconnected when using debugwire. ? all external reset sources must be disconnected. 20.4 software break points debugwire supports program memory break points by the avr break instruction. setting a break point in avr studio ? will insert a break instruction in the program memo ry. the instruc- tion replaced by the break instru ction will be stored. when program execution is continued, the stored instruction will be execut ed before continuing from the program memory. a break can be inserted manually by putting the break instruction in the program. the flash must be re-programmed each time a break point is changed. this is automatically handled by avr studio th rough the debugwire inte rface. the use of brea k points will therefore reduce the flash data retention. devices used for debugging purposes should not be shipped to end customers. 20.5 limitations of debugwire the debugwire communication pin (dw) is physica lly located on the same pin as external reset (reset). an external reset source is therefore not supported when the debugwire is enabled. the debugwire system accurately emulates all i/ o functions when running at full speed, i.e., when the program in the cpu is running. when the cpu is stopped, care must be taken while accessing some of the i/o registers via the debugger (avr studio). a programmed dwen fuse enable s some parts of the clock system to be running in all sleep modes. this will increase the power consumption while in sleep. thus, the dwen fuse should be disabled when debugwire is not used. 20.6 register description the following section describes the registers used with the debugwire. 20.6.1 dwdr ? debugwire data register the dwdr register provides a communication channel from the running program in the mcu to the debugger. this register is only accessible by the debugwire and can therefore not be used as a general purpose register in the normal operations. bit 76543210 0x20 (0x40) dwdr[7:0] dwdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 166 7753f?avr?01/11 attiny261/attiny461/attiny861 21. self-programming the flash the device provides a self-programming me chanism for downloading and uploading program code by the mcu itself. the self-programming ca n use any available data interface and associ- ated protocol to read code and write (program) that code into the program memory. the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buf- fer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a page erase and a page write operation: alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the bu ffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be re-written. when using alternative 1, the boot loader provides an effective read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alter- native 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase a nd page write operation is addressing the same page. 21.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?00000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? the cpu is halted during the page erase operation. 21.2 filling the temporar y buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto-erase after a page write operation or by writing the ctpb bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an spm page load operation, all data loaded will be lost. 167 7753f?avr?01/11 attiny261/attiny461/attiny861 21.3 performing a page write to execute page write, set up the address in the z-pointer, write ?00000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. ? the cpu is halted during the page write operation. 21.4 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see table 22-7 on page 174 ), the program counter can be treated as having two different sections. one sect ion, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is shown in figure 21-1 . note that the page erase and page write operations are addressed independently. therefore it is of major importance that the software addresses the same page in both the page erase and page write operation. the lpm instruction uses the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. figure 21-1. addressing the flash during spm (1) note: 1. the different variables used in figure 21-1 are listed in table 22-7 on page 174 . bit 1514131211109 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30)z7z6z5z4z3z2z1z0 76543210 program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 168 7753f?avr?01/11 attiny261/attiny461/attiny861 21.4.1 eeprom write prevents writing to spmcsr note that an eeprom write oper ation will block all software progra mming to flash. reading the fuses and lock bits from software will also be prevented during the eeprom write operation. it is recommended that the user checks the status bit (eepe) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. 21.4.2 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the rflb and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after t he rflb and spmen bits are set in spmcsr, the value of the lock bits will be loaded in the des tination register. the rflb and spmen bits will auto-clear upon completion of reading the lock bits or if no lpm instruction is executed within three cpu cycles or no spm instruction is ex ecuted within four cpu cycles. when rflb and spmen are cleared, lpm will work as de scribed in the inst ruction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the rflb and spmen bits in spmcsr. when an lpm instruction is executed within three cycles after the rflb and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 22-5 on page 173 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. when an lpm instruc- tion is executed within three cycles after the rflb and spmen bits are set in the spmcsr, the value of the fuse high byte (fhb) will be l oaded in the destination register as shown below. refer to table xxx on page xxx for detailed description and mapping of the fuse high byte. fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. 21.4.3 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situ ations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instruct ions incorrectly, if the supply voltage for executing instructions is too low. bit 76543210 rd ??????lb2lb1 bit 7654 3210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 7654 3210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 169 7753f?avr?01/11 attiny261/attiny461/attiny861 flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. keep the avr reset active (low) during peri ods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating volt- age matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 2. keep the avr core in power-down sleep mode during periods of low v cc . this will pre- vent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 21.4.4 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 21-1 shows the typical pro- gramming time for flash accesses from the cpu. note: 1. minimum and maximum programming time is per individual operation. 21.5 register description 21.5.1 spmcsr ? store program memory control and status register the store program memory control and status register contains the control bits needed to con- trol the program memory operations. ? bits 7:6 ? res: reserved bits these bits are reserved bits in the attiny261/461/861 and always read as zero. ? bit 5 ? sigrd: signature row read if this bit is written to one at the same time as spmen, the next lpm instruction within three clock cycles will read a byte from the signature row in to the dest ination register for details. an spm instruction within four cycles after sigrd and spm en are set will have no effect. ? bit 4 ? ctpb: clear temporary page buffer if the ctpb bit is writte n while filling the temporary page bu ffer, the temporary page buffer will be cleared and the da ta will be lost. ? bit 3 ? rflb: read fuse and lock bits an lpm instruction within three cycles after rflb and spmen are set in the spmcsr register, will read either the lock bits or t he fuse bits (depending on z0 in the z-pointer) in to the destina- tion register. see ?eeprom write preven ts writing to spmcsr? on page 168 for details. table 21-1. spm programming time (1) symbol min programming time max programming time flash write (page erase, page write, and write lock bits by spm) 3.7 ms 4.5 ms bit 7 6 5 4 3 2 1 0 0x37 (0x57) ?? sigrd ctpb rflb pgwrt pgers spmen spmcsr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 170 7753f?avr?01/11 attiny261/attiny461/attiny861 ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon co mpletion of a page write, or if no spm instruction is ex ecuted within four clock cycles. the cpu is halted during the entire page write operation. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bi t will auto-clear upon comp letion of a page erase, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation. ? bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next four clock cycles. if written to one together with either ctpb, rflb, pgwrt, or pgers, the following spm instruction will have a special meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will aut o-clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. 171 7753f?avr?01/11 attiny261/attiny461/attiny861 22. memory programming this section describes the different methods for programming the attiny261/461/861 memories. 22.1 program and data memory lock bits the attiny261/461/861 provides two lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional security listed in table 22-2 . the lock bits can only be erased to ?1? with the chip erase command. the attiny261/461/861 has no separate boot loader section. the spm instruction is enabled for the whole flash, if the selfprogen fuse is programmed (?0?), otherwise it is disabled. note: 1. ?1? means unprogrammed, ?0? means programmed notes: 1. program the fuse bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed table 22-1. lock bit byte (1) lock bit byte bit no desc ription default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) 5 ? 1 (unprogrammed) 4 ? 1 (unprogrammed) 3 ? 1 (unprogrammed) 2 ? 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 22-2. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in high-voltage and serial programming mode. the fuse bits are locked in both serial and high-voltage programming mode. (1) 300 further programming and verifica tion of the flash and eeprom is disabled in high-voltage and serial programming mode. the fuse bits are locked in both serial and high-voltage programming mode. (1) 172 7753f?avr?01/11 attiny261/attiny461/attiny861 22.2 fuse bytes the attiny261/461/861 has three fuse bytes. table 22-3 , table 22-4 and table 22-5 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. notes: 1. see ?alternate functions of port b? on page 63 for description of rstdisbl and dwen fuses. 2. dwen must be unprogrammed when lock bit security is required. see ?program and data memory lock bits? on page 171. 3. the spien fuse is not accessible in spi programming mode. 4. see ?wdtcr ? watchdog timer control register? on page 46 for details. 5. see table 23-4 on page 190 for bodlevel fuse decoding. 6. when programming the rstdisbl fuse, high-voltage serial programming has to be used to change fuses to perform further programming. table 22-3. fuse extended byte fuse high byte bit no d escription default value 7 - 1 (unprogrammed) 6 - 1 (unprogrammed) 5 - 1 (unprogrammed) 4 - 1 (unprogrammed) 3 - 1 (unprogrammed) 2 - 1 (unprogrammed) 1 - 1 (unprogrammed) selfprgen 0 self-programming enable 1 (unprogrammed) table 22-4. fuse high byte fuse high byte bit no d escription default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen (2) 6 debugwire enable 1 (unprogrammed) spien (3) 6 enable serial program and data downloading 0 (programmed, spi prog. enabled) wdton (4) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) bodlevel2 (5) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (5) 1 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (5) 0 brown-out detector trigger level 1 (unprogrammed) 173 7753f?avr?01/11 attiny261/attiny461/attiny861 notes: 1. see ?system clock prescaler? on page 32 for details. 2. the ckout fuse allows the system clock to be output on portb5. see ?c lock output buffer? on page 30 for details. 3. the default value of sut1..0 results in maximum start-up time for the default clock source. see table 7-7 on page 29 for details. 4. the default setting of cksel3..0 results in internal rc oscillator @ 8.0 mhz. see table 7-6 on page 29 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 22.2.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuse s are also latched on power-up in normal mode. 22.3 signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and high-voltage programming mode, also when the device is locked. the three bytes reside in a separat e address space. the attiny261/461/861signature bytes are given in table 22-6 . 22.4 calibration byte signature area of the attiny261/461/861 has one byte of calibration data for the internal rc oscillator. this byte resides in the high byte of address 0x000. during reset, this byte is auto- matically written into the osccal register to ensure correct frequency of the calibrated rc oscillator. table 22-5. fuse low byte fuse low byte bit no description default value ckdiv8 (1) 7 divide clock by 8 0 (programmed) ckout (2) 6 clock output enable 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (3) sut0 4 select start-up time 0 (programmed) (3) cksel3 3 select clock source 0 (programmed) (4) cksel2 2 select clock source 0 (programmed) (4) cksel1 1 select clock source 1 (unprogrammed) (4) cksel0 0 select clock source 0 (programmed) (4) table 22-6. device id parts signature bytes address 0x000 0x001 0x002 attiny261 0x1e 0x91 0x0c attiny461 0x1e 0x92 0x08 attiny861 0x1e 0x93 0x0d 174 7753f?avr?01/11 attiny261/attiny461/attiny861 22.5 reading the signat ure row from software to read the signature row from software, load the z-pointer with the signature byte address given in table 22-6 on page 173 and set the sigrd and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after the sigrd and spmen bits are set in spmcsr, the signature byte valu e will be loaded in the destin ation register. the sigrd and spmen bits will auto-clear upon completion of re ading the signature row lo ck bits or if no lpm instruction is executed within three cpu cycles. when sigrd and spmen are cl eared, lpm will work as described in the instruction set manual. note: before attempting to se t spmen it is important to test this bit is cleared showing that the hardware is ready for a new operation. 22.6 page size 22.7 parallel programming paramete rs, pin mapping, and commands this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the attiny261/461/861. pulses are assumed to be at least 250 ns unless otherwise noted. 22.7.1 signal names in this section, some pins of the attiny261 /461/861 are referenced by signal names describing their functionality during parallel programming, see figure 22-1 and table 22-9 . pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a positive pulse. the bit coding is shown in table 22-11 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are shown in table 22-12 . table 22-7. no. of words in a page and no. of pages in the flash device flash size page size pc word no. of pages pcpage pcmsb attiny261 1k words (2k bytes) 16 words pc[3:0] 64 pc[9:4] 9 attiny461 2k words (4k bytes) 32 words pc[4:0] 64 pc[10:5] 10 attiny861 4k words (8k bytes) 32 words pc[4:0] 128 pc[11:5] 11 table 22-8. no. of words in a page and no. of pages in the eeprom device eeprom size page size pcword no. of pages pcpage eeamsb attiny261 128 bytes 2 by tes eea[1:0] 64 eea[6:2] 6 attiny461 256 bytes 4 by tes eea[1:0] 64 eea[7:2] 7 attiny861 512 bytes 4 by tes eea[1:0] 128 eea[8:2] 8 175 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 22-1. parallel programming table 22-9. pin name mapping signal name in programming mode pin name i/o function wr pb0 i write pulse (active low). xa0 pb1 i xtal action bit 0 xa1/bs2 pb2 i xtal action bit 1. byte select 2 (?0? selects low byte, ?1? selects 2?nd high byte). pagel/bs1 pb3 i byte select 1 (?0? selects low byte, ?1? selects high byte). program memory and eeprom data page load. oe pb5 i output enable (active low). rdy/bsy pb6 o 0: device is busy programming, 1: device is ready for new command. data i/o pa7-pa0 i/o bi-directional data bus (output when oe is low). table 22-10. pin values used to enter programming mode pin symbol value pagel/bs1 prog_enable[3] 0 xa1/bs2 prog_enable[2] 0 xa0 prog_enable[1] 0 wr prog_enable[0] 0 table 22-11. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle vcc +5v gnd xt al1/pb4 pb6 pb5 pb0 pb3 pb1 pb2 pa7 - pa0 data reset +12 v pagel/bs1 xa0 xa1/bs2 oe rdy/bsy wr avcc +5v 176 7753f?avr?01/11 attiny261/attiny461/attiny861 22.8 parallel programming 22.8.1 enter programming mode the following algorithm puts the devi ce in parallel programming mode: 1. apply 4.5 - 5.5v between v cc and gnd. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 22-10 on page 175 to ?0000? and wait at least 100 ns. 4. apply 11.5 - 12.5v to reset . any activity on prog_enable pins within 100 ns after +12v has been applied to reset , will cause the device to fail entering programming mode. 5. wait at least 50 s before sending a new command. 22.8.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. ? address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. 22.8.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be perfor med before the flas h and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved duri ng chip erase if the eesave fuse is programmed. table 22-12. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom 177 7753f?avr?01/11 attiny261/attiny461/attiny861 load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this starts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. 22.8.4 programming the flash the flash is organized in pages, see table 22-7 on page 174 . when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be pro- grammed simultaneously. the following procedure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. 1. e. latch data 2. set bs1 to ?1?. this selects high data byte. 3. give pagel a positive pulse. this latches the data bytes. (see figure 22-3 for signal waveforms) f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. 178 7753f?avr?01/11 attiny261/attiny461/attiny861 while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash . this is illustrated in figure 22-2 on page 178 . note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. program page 1. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 22-3 for signal waveforms). i. repeat b through h until the entire flas h is programmed or until all data has been programmed. j. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads th e command, and the internal write signals are reset. figure 22-2. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 22-7 on page 174 . program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 179 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 22-3. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters re fer to the programming description above. 22.8.5 programming the eeprom the eeprom is organized in pages, see table 22-8 on page 174 . when programming the eeprom, the program data is latche d into a page buffer. this al lows one page of data to be programmed simultaneously. th e programming algorithm for th e eeprom data memory is as follows (refer to ?programming the flash? on page 177 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled. l: program eeprom page 1. set bs to ?0?. 2. give wr a negative pulse. this starts prog ramming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 22-4 for signal waveforms). rdy/bsy wr oe reset +12v 0x10 addr. low addr. high data data low data high addr. low data low data high xa1/bs2 xa0 pagel/bs1 xtal1 xx xx xx abcdeb cdegh f 180 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 22-4. programming the eeprom waveforms 22.8.6 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 177 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. 22.8.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 177 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. 22.8.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 177 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. rdy/bsy wr oe reset +12v 0x11 addr. high data addr. low data addr. low data xx xa1/bs2 xa0 pagel/bs1 xtal1 xx agbceb c el k 181 7753f?avr?01/11 attiny261/attiny461/attiny861 22.8.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 177 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 22.8.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?programming the flash? on page 177 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. 4. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2 to ?0?. this selects low data byte. figure 22-5. programming the fuses waveforms 22.8.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 177 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. rdy/bsy wr oe reset +12v 0x40 data data xx xa1/bs2 xa0 pagel/bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte 182 7753f?avr?01/11 attiny261/attiny461/attiny861 22.8.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 177 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. figure 22-6. mapping between bs1, bs2 and the fuse and lock bits during read 22.8.13 reading the signature bytes the algorithm for reading the signatur e bytes is as follows (refer to ?programming the flash? on page 177 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 22.8.14 reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to ?programming the flash? on page 177 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. lock bits 0 1 bs2 fuse high byte 0 1 bs1 data fuse low byte 0 1 bs2 extended fuse byte 183 7753f?avr?01/11 attiny261/attiny461/attiny861 22.9 serial downloading both the flash and eeprom memo ry arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (out- put). after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note, in table 22-13 on page 183 , the pin mapping for spi programming is listed. not all pa rts use the spi pins dedicated for the internal spi interface. figure 22-7. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscilla tor, it is no need to connect a clock source to the clki pin. when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be present. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz high: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz table 22-13. pin mapping serial programming symbol pins i/o description mosi pb0 i serial data in miso pb1 o serial data out sck pb2 i serial clock vcc gnd sck miso mosi reset +1.8 - 5.5v 184 7753f?avr?01/11 attiny261/attiny461/attiny861 22.9.1 serial programming algorithm when writing serial data to the attiny261/461/86 1, data is clocked on the rising edge of sck. when reading data from the attiny261/461/861, dat a is clocked on the falling edge of sck. see figure 23-6 and figure 23-7 for timing details. to program and verify the attiny261/461/861 in the serial programming mode, the following sequence is recommended (see four byte instruction formats in table 22-15 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some sys- tems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programming by sending the programming enable serial instruction to pin mosi. 3. the serial programming instru ctions will not work if the co mmunication is out of synchro- nization. when in sync. the second byte (0x53), will echo ba ck when issuing the third byte of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitte d. if the 0x53 did no t echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 5 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the write program memory page instruction with the 6 msb of the address. if polling (rdy/bsy) is not used, the user must wait at least t wd_flash before issuing the next page. (see table 22-14 .) accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. a: the eeprom array is programmed one byte at a time by supplying the address and data together with the app ropriate write instruction. an eeprom memory location is first automatically erased before new da ta is written. if polling (rdy/bsy) is not used, the user must wait at least t wd_eeprom before issuing the next byte. (see table 22-14 .) in a chip erased device, no 0xffs in the data file(s) need to be programmed. b: the eeprom array is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 2 lsb of the address and data together with the load eeprom memory page instruction. the eeprom memory page is stored by loading the write eeprom memory page instruction wit h the 6 msb of the ad dress. when using eeprom page access on ly byte locations loaded with the load eeprom memory page instruction is altered. the remaining loca tions remain unchanged. if polling (rdy/bsy) is not used, the used must wait at least t wd_eeprom before issuing the next page (see table 22-8 ). in a chip erased device, no 0xff in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the con- tent at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. tu r n v cc power off. 185 7753f?avr?01/11 attiny261/attiny461/attiny861 22.9.2 serial programming instruction set table 22-15 on page 185 and figure 22-8 on page 186 describes the instruction set. table 22-14. minimum wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5 ms t wd_eeprom 4.0 ms t wd_erase 4.0 ms t wd_fuse 4.5 ms table 22-15. serial programming instruction set instruction/operation instruction format byte 1 byte 2 byte 3 byte4 programming enable $ac $53 $00 $00 chip erase (program memory/eeprom) $ac $80 $00 $00 poll rdy/bsy $f0 $00 $00 data byte out load instructions load extended address byte (1) $4d $00 extended adr $00 load program memory page, high byte $48 adr msb adr lsb high data byte in load program memory page, low byte $40 adr msb adr lsb low data byte in load eeprom memory page (page access) $c1 $00 0000 000aa data byte in read instructions read program memory, high byte $28 adr msb adr lsb high data byte out read program memory, low byte $20 adr msb adr lsb low data byte out read eeprom memory $a0 $00 00aa aaaa data byte out read lock bits $58 $00 $00 data byte out read signature byte $30 $00 0000 000aa data byte out read fuse bits $50 $00 $00 data byte out read fuse high bits $58 $08 $00 data byte out read extended fuse bits $50 $08 $00 data byte out read calibration byte $38 $00 $00 data byte out write instructions (6) write program memory page $4c adr msb adr lsb $00 write eeprom memory $c0 $00 00aa aaaa data byte in write eeprom memory page (page access) $c2 $00 00aa aa00 $00 write lock bits $ac $e0 $00 data byte in 186 7753f?avr?01/11 attiny261/attiny461/attiny861 notes: 1. not all instructions are applicable for all parts. 2. a = address 3. bits are programmed ?0?, unprogrammed ?1?. 4. to ensure future compatibility, unused fuses and lock bits should be unprogrammed (?1?). 5. refer to the corresponding section for fuse and lock bits, calibration and signature bytes and page size. 6. instructions accessing program memory use a word address. this address may be random within the page range. 7. see http://www.atmel.com/avr for application notes regarding programming and programmers. if the lsb in rdy/bsy data byte out is ?1?, a pr ogramming operation is still pending. wait until this bit returns ?0? before the ne xt instruction is carried out. within the same page, the low data byte must be loaded prior to the high data byte. after data is loaded to the page buf fer, program the eeprom page, see figure 22-8 on page 186 . figure 22-8. serial programming instruction example write fuse bits $ac $a0 $00 data byte in write fuse high bits $ac $a8 $00 data byte in write extended fuse bits $ac $a4 $00 data byte in table 22-15. serial programming instruction set (continued) instruction/operation instruction format byte 1 byte 2 byte 3 byte4 byte 1 byte 2 byte 3 byte 4 adr lsb bit 15 b 0 serial programming instruction program memory/ eeprom memory page 0 page 1 page 2 page n-1 page buffer write program memory page/ write eeprom memory page load program memory page (high/low byte)/ load eeprom memory page (page access) byte 1 byte 2 byte 3 byte 4 bit 15 b 0 adr msb page offset page number ad r m ms sb a a adr r l lsb b 187 7753f?avr?01/11 attiny261/attiny461/attiny861 23. electrical characteristics 23.1 absolute maximum ratings* notes: 1. maximum current per port = 30ma 23.2 dc characteristics operating temperature..................................?55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .....................................?65c to +150c voltage on any pin except reset with respect to ground ...............................?0.5v to v cc +0.5v voltage on reset with respect to ground..... ?0.5v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ................................................ 40.0ma dc current v cc and gnd pins................................. 200.0ma injection current at vcc=0v ... ................................. 5.0ma (1) injection current at vcc=5v ...... ................................. 1.0ma t a = ?40c to +125c, v cc = 2.7v to 5.5v (unless otherwise noted) (1) symbol parameter condition min. typ. max. units v il input low-voltage except xtal1 and reset pin ?0.5 0.2v cc v v ih input high-voltage except xtal1 and reset pin 0.7v cc (3) v cc +0.5 v v il1 input low-voltage xtal1 pin, external clock selected ?0.5 0.1v cc v v ih1 input high-voltage xtal1 pin, external clock selected 0.8v cc (3) v cc +0.5 v v il2 input low-voltage reset pin ?0.5 0.2v cc v v ih2 input high-voltage reset pin 0.9v cc (3) v cc +0.5 v v il3 input low-voltage reset pin as i/o ?0.5 0.2v cc v v ih3 input high-voltage reset pin as i/o 0.7v cc (3) v cc +0.5 v v ol output low voltage (4) (except reset pin) i ol = 10ma, v cc = 5v i ol = 5ma, v cc = 3v 0.6 0.5 v v v oh output high-voltage (5) (except reset pin) i oh = ?10ma, v cc = 5v i oh = ?5ma, v cc = 3v 4.3 2.5 v v i il input leakage current i/o pin vcc = 5.5 v, pin low (absolute value) 250 na i ih input leakage current i/o pin vcc = 5.5 v, pin high (absolute value) 250 na r rst reset pull-up resistor 30 60 k r pu i/o pin pull-up resistor 20 50 k 188 7753f?avr?01/11 attiny261/attiny461/attiny861 notes: 1. all dc characteristics contained in this data sheet are based on simulation and charac terization of attiny261/461/861 a vr microcontrollers manufactured in a typical process technology. these values are preliminary values representing design tar- gets, and will be updated after characterization of actual automotive silicon. 2. ?max? means the highest value where the pin is guaranteed to be read as low. 3. ?min? means the lowest value where t he pin is guaranteed to be read as high. 4. although each i/o port can sink more than the test conditions (10ma at v cc = 5v, 5ma at v cc = 3v) under steady state con- ditions (non-transient), the following must be observed: 1] the sum of all iol, for a ll ports, should not exceed 60ma. if iol exceeds the test condition, vol may exceed the related sp ecification. pins are not guar anteed to sink current greater than the listed test condition. 5. although each i/o port can source mo re than the test conditions (10ma at v cc = 5v, 5ma at v cc = 3v) under steady state conditions (non-transient), th e following must be observed: 1] the sum of all ioh, for a ll ports, should not exceed 60ma. if ioh exceeds the test condition, voh ma y exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 6. values using methods described in ?minimizing power consumption? on page 36 . power reduction is enabled (prr = 0xff) and there is no i/o drive. 7. bod disabled. i cc power supply current active 4mhz, v cc = 3v (6) atd on 1.45 2 ma active 8mhz, v cc = 5v (6) atd on 3.96 6 ma active 16mhz, v cc = 5v (6) atd on 7.16 10 ma idle 4mhz, v cc = 3v (6) 0.25 0.4 ma idle 8mhz, v cc = 5v (6) 0.96 1.2 ma idle 16mhz, v cc = 5v (6) 1.91 2.5 ma power-down mode wdt enabled, v cc = 3v (7) 450a wdt disabled, v cc = 3v (7) 0.12 30 a wdt enabled, v cc = 5v (7) 675a wdt disabled, v cc = 5v (7) 0.13 45 a v acio analog comparator input offset voltage v cc = 5v, 0.1v cc 190 7753f?avr?01/11 attiny261/attiny461/attiny861 23.4.3 external clock drive 23.5 system and reset characteristics notes: 1. values are guidelines only. table 23-2. external clock drive symbol parameter v cc = 2.7 - 5.5v v cc = 4.5 - 5.5v units min. max. min. max. 1/t clcl clock frequency 0 8 0 16 mhz t clcl clock period 125 62.5 ns t chcx high time 40 20 ns t clcx low time 40 20 ns t clch rise time 1.6 0.5 s t chcl fall time 1.6 0.5 s t clcl change in period from one clock cycle to the next 2 2 % table 23-3. reset, brown-out and internal voltage characteristics (1) symbol parameter condition min typ max units t rst minimum pulse width on reset pin v cc = 3v 2.5 s v hyst brown-out detector hysteresis 50 mv t bod min pulse width on brown-out reset 2s v bg bandgap reference voltage v cc = 3.0v, t a =25c 1.0 1.1 1.2 v t bg bandgap reference start-up time v cc = 2.7v, t a =25c 40 70 s i bg bandgap reference current consumption v cc = 2.7v, t a =25c 15 a table 23-4. bodlevel fuse coding (1) bodlevel [2..0] fuses min v bot typ v bot max v bot units 111 bod disabled 110 1.68 1.8 1.92 v 101 2.5 2.7 2.9 100 4.0 4.3 4.6 011 reserved 010 001 000 note: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guar- antees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guaranteed. 191 7753f?avr?01/11 attiny261/attiny461/attiny861 23.6 adc characteristics table 23-5. adc characteristics, single ended channels, -40c +125c symbol parameter condi tion min typ max units resolution single ended conversion 10 bits tue absolute accuracy v cc = 4v, v ref = 4v, adc clock = 200 khz 2.0 4.0 lsb inl integral non-linearity v cc = 4v,v ref = 4v, adc clock = 200 khz 0.6 1.8 lsb dnl differential non-linearity (dnl) v cc = 4v, v ref = 4v, adc clock = 200 khz 0.2 0.6 lsb gain error v cc = 4v, v ref = 4v, adc clock = 200 khz -5.0 -2.0 3.0 lsb offset error v cc = 4v, v ref = 4v, adc clock = 200 khz -3.5 1.2 3.5 lsb v ref external reference voltage 2.56 avcc v clock frequency 50 200 khz avcc analog supply frequency v cc - 0.3 v cc + 0.3 v v int internal voltage reference 1.0 1.1 1.2 v r ain analog input resistance 100 m r ref reference input resistance 21 30 39 k temperature sensor accuracy after firmware calibration internal v ref v cc = 3v 10 c 192 7753f?avr?01/11 attiny261/attiny461/attiny861 table 23-6. adc characteristics, differe ntial channels, -40c +125c symbol parameter condition min typ max units resolution differential conversion, gain = 1x or 8x 8 bits differential conversion, gain = 20x or 32x 8 tue absolute accuracy gain = 1x / 8x, bipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 1.7 4.0 lsb gain = 20x / 32x, bipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 2.0 5.0 gain = 1x / 8x, unipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 2.3 5.0 gain = 20x / 32x, unipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 3.0 6.0 inl integral non-linearity gain = 1x / 8x, bipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 0.3 1.5 lsb gain = 20x / 32x, bipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 0.7 3.0 gain = 1x / 8x, unipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 1.0 3.0 gain = 20x / 32x, unipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 2.0 6.0 dnl differential non-linearity gain = 1x / 8x, bipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 0.3 1.0 lsb gain = 20x / 32x, bipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 0.4 1.2 gain = 1x / 8x, unipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 0.4 1.0 gain = 20x / 32x, unipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz 0.8 2.5 193 7753f?avr?01/11 attiny261/attiny461/attiny861 gain error gain = 1x / 8x, bipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz -4.0 2.0 4.0 lsb gain = 20x / 32x, bipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz -4.0 1.4 4.0 gain = 1x / 8x, unipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz -5.0 -2.6 5.0 gain = 20x / 32x, unipolar, v cc = 5v, v ref = 4v, adc clock = 200 khz -5.0 -0.8 5.0 offset error gain = 1x, v cc = 5v, v ref = 4v, adc clock = 200 khz -3.0 0.6 3.0 lsb v ref external reference voltage 2.56 avcc-0.5 v table 23-6. adc characteristics, dif ferential channels, -40c +125c (continued) symbol parameter condition min typ max units 194 7753f?avr?01/11 attiny261/attiny461/attiny861 23.7 parallel programmi ng characteristics figure 23-3. parallel programming timing, including some general timing requirements figure 23-4. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 23-3 (i.e., t dvxh , t xhxl , and t xldx ) also apply to load- ing operation. data & contol (data, xa0, xa1/bs2, pagel/bs1) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy t plbx t bvph t xlwl t wlbx t bvwl wlrl xtal1 xlxh t addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data pagel/bs1 xa0 xa1/bs2 load address (low byte) load data (low byte) load data (high byte) load address (low byte) 195 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 23-5. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in figure 23-3 (i.e., t dvxh , t xhxl , and t xldx ) also apply to read- ing operation. notes: 1. t wlrh is valid for the write flash, write eepro m, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. table 23-7. parallel programming characteristics, v cc = 5v 10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (1) 3.7 4.5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 9 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data pagel/bs1 xa0 xa1/bs2 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz 196 7753f?avr?01/11 attiny261/attiny461/attiny861 23.8 serial programming characteristics figure 23-6. serial programming waveforms figure 23-7. serial programming timing note: 1. 2 t clcl for f ck < 12 mhz, 3 t clcl for f ck >= 12 mhz table 23-8. serial programming characteristics, t a = -40c to 125c, v cc = 2.7 - 5.5v (unless otherwise noted) symbol parameter min typ max units 1/t clcl oscillator frequency (attiny261/461/861v) 0 4 mhz t clcl oscillator period (attiny261/461/861v) 250 ns 1/t clcl oscillator frequency (attiny261/461/861l, vcc = 2.7 - 5.5v) 010mhz t clcl oscillator period (attiny261/461/861l, vcc = 2.7 - 5.5v) 100 ns 1/t clcl oscillator frequency (attiny261/461/861, v cc = 4.5v - 5.5v) 016mhz t clcl oscillator period (attiny261/461/861, v cc = 4.5v - 5.5v) 50 ns t shsl sck pulse width high 2 t clcl* ns t slsh sck pulse width low 2 t clcl * ns t ovsh mosi setup to sck high t clcl ns t shox mosi hold after sck high 2 t clcl ns t sliv sck low to miso valid tbd tbd tbd ns msb msb lsb lsb serial clock input (sck) serial data input (mosi) (miso) sample serial data output mosi miso sck t ovsh t shsl t slsh t shox t sliv 197 7753f?avr?01/11 attiny261/attiny461/attiny861 24. typical characteristics the data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. these values are preliminary values representing design targets, and will be updated after char acterization of actual automotive silicon. thus, the data should be tr eated as indications of how the part will behave. the following charts show typical behavior. t hese figures are not tested during manufacturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient tempera- ture. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential cur- rent drawn by the watchdog timer. unless otherwise specified the data contained in this chapter are for -40c to +85c. 24.1 active supply current figure 24-1. active supply current vs. low frequency (0.1 - 1.0 mhz) 198 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 24-2. active supply current vs. frequency (1 - 16 mhz) 24.2 idle supply current figure 24-3. idle supply current vs. frequency (1 - 16 mhz) 199 7753f?avr?01/11 attiny261/attiny461/attiny861 24.3 supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduction register. see ?prr ? power reduction register? on page 38 for details. it is possible to calculate the typical current consumption based on the numbers from table 24-1 for other v cc and frequency settings than listed in table 24-2 . 24.3.1 example calculate the expected current consumption in idle mode with timer0, adc, and usi enabled at v cc = 2.0v and f = 1mhz. from table 24-2 , third column, we see that we need to add 10% for the timer0, 27.3% for the adc, and 6.5% for the usi module. reading from figure 24-3 on page 198 , we find that the idle current consumption is ~0,085 ma at v cc = 2.0v and f=1mhz. the total current consumption in idle mode with timer0, adc, and usi enabled, gives: table 24-1. additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prtim1 65 ua 423 ua 1787 ua prtim0 7 ua 39 ua 165 ua prusi 5 ua 25 ua 457 ua pradc 18 ua 111 ua 102 ua table 24-2. additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 24-1 on page 197 and figure 24-2 on page 198 ) additional current consumption compared to idle with external clock prtim1 26.9% 103.7% prtim0 2.6% 10.0% prusi 1.7% 6.5% pradc 7.1% 27.3% i cc total 0.085 ma 1 0.10 0.273 0.065 ++ + () ? 0.122 ma ? 200 7753f?avr?01/11 attiny261/attiny461/attiny861 24.4 power-down supply current figure 24-4. power-down supply current vs. v cc (watchdog timer disabled) figure 24-5. power-down supply current vs. v cc (watchdog timer enabled) 201 7753f?avr?01/11 attiny261/attiny461/attiny861 24.5 pin pull-up figure 24-6. i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 24-7. reset pull-up resistor curr ent vs. reset pin voltage (v cc = 5v) 202 7753f?avr?01/11 attiny261/attiny461/attiny861 24.6 pin driver strength figure 24-8. i/o pin output voltage vs. sink current (v cc = 3v) figure 24-9. i/o pin output voltage vs. sink current (v cc = 5v) 203 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 24-10. i/o pin output voltage vs. source current (v cc = 3v) figure 24-11. i/o pin output voltage vs. source current (v cc = 5v) 204 7753f?avr?01/11 attiny261/attiny461/attiny861 24.7 pin threshold and hysteresis figure 24-12. i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 24-13. i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 205 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 24-14. reset input threshold voltage vs. v cc (v ih , reset read as ?1?) figure 24-15. reset input threshold voltage vs. v cc (v il , reset read as ?0?) 206 7753f?avr?01/11 attiny261/attiny461/attiny861 24.8 bod threshold and analog comparator offset figure 24-16. bod threshold vs. temperature (bod level is 4.3v) figure 24-17. bod threshold vs. temperature (bod level is 2.7v) 207 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 24-18. bod threshold vs. temperature (bod level is 1.8v) 24.9 internal oscillator speed figure 24-19. watchdog oscillator freq uency vs. temperature 208 7753f?avr?01/11 attiny261/attiny461/attiny861 figure 24-20. calibrated 8.0 mhz rc oscillato r frequency vs. temperature 209 7753f?avr?01/11 attiny261/attiny461/attiny861 25. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f (0x5f) sreg i t h s v n z c page 11 0x3e (0x5e) sph ? ? ? ? ? sp10 sp9 sp8 page 13 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 13 0x3c (0x5c) reserved ? 0x3b (0x5b) gimsk int1 int0 pcie1 pcie0 ? ? ? ? page 53 0x3a (0x5a) gifr intf1 intf0 pcif ? ? ? ? ? page 53 0x39 (0x59) timsk ocie1d ocie1a ocie1b ocie0a ocie0b toie1 toie0 ticie0 page 87 , page 125 0x38 (0x58) tifr ocf1d ocf1a oc f1b ocf0a ocf0b tov1 tov0 icf0 page 88 , page 126 0x37 (0x57) spmcsr ? ? sigrd ctpb rflb pgwrt pgers spmen page 169 0x36 (0x56) prr prtim1 prtim0 prusi pradc page 36 0x35 (0x55) mcucr ?pudsesm1sm0 ?isc01isc00 page 38 , page 69 , page 52 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf page 45 , 0x33 (0x53) tccr0b ? ? ? tsm psr0 cs02 cs01 cs00 page 71 0x32 (0x52) tcnt0l timer/counter0 counter register low byte page 86 0x31 (0x51) osccal oscillat or calibration register page 32 0x30 (0x50) tccr1a com1a1 com1a0 com1b1 com1b0 foc1a foc1b pwm1a pwm1b page 115 0x2f (0x4f) tccr1b pwm1x psr1 dtps11 dtps10 cs13 cs12 cs11 cs10 page 169 0x2e (0x4e) tcnt1 timer/counter1 counter register page 123 0x2d (0x4d) ocr1a timer/counter1 output compare register a page 124 0x2c (0x4c) ocr1b timer/counter1 output compare register b page 124 0x2b (0x4b) ocr1c timer/counter1 output compare register c page 124 0x2a (0x4a) ocr1d timer/counter1 output compare register d page 125 0x29 (0x49) pllcsr lsm pcke plle plock page 90 0x28 (0x48) clkpr clkpce clkps3 clkps2 clkps1 clkps0 page 33 0x27 (0x47) tccr1c com1a1s com1a0s co m1b1s com1b0s com1d1 com1d0 foc1d pwm1d page 119 0x26 (0x46) tccr1d fpie1 fpen1 fpnc1 fpes1 fpac1 fpf1 wgm11 wgm10 page 121 0x25 (0x45) tc1h tc19 tc18 page 123 0x24 (0x44) dt1 dt1h3 dt1h2 dt1h1 dt1h0 dt1l3 dt1l2 dt1l1 dt1l0 page 127 0x23 (0x43) pcmsk0 pcint7 pcint6 pcin t5 pcint4 pcint3 pcint2 pcint1 pcint0 page 54 0x22 (0x42) pcmsk1 pcint15 pcint14 pcin t13 pcint12 pcint11 pcint10 pcint9 pcint8 page 54 0x21 (0x41) wdtcr wdif wdi e wdp3 wdce wde wdp2 wdp1 wdp0 page 46 0x20 (0x40) dwdr dwdr[7:0] page 36 0x1f (0x3f) eearh eear8 page 22 0x1e (0x3e) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 page 22 0x1d (0x3d) eedr eeprom data register page 23 0x1c (0x3c) eecr ? ? eepm1 eepm0 eerie eempe eepe eere page 23 0x1b (0x3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 page 69 0x1a (0x3a) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 page 69 0x19 (0x39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 page 69 0x18 (0x38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 page 69 0x17 (0x37) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 69 0x16 (0x36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 69 0x15 (0x35) tccr0a tcw0 icen0 icnc0 ices0 acic0 ctc0 page 85 0x14 (0x34) tcnt0h timer/counter0 counter register high byte page 86 0x13 (0x33) ocr0a timer/counter0 output compare register a page 86 0x12 (0x32) ocr0b timer/counter0 output compare register b page 86 0x11 (0x31) usipp usipos page 139 0x10 (0x30) usibr usi buffer register page 136 0x0f (0x2f) usidr usi data register page 135 0x0e (0x2e) usisr usisif usioif usipf u sidc usicnt3 usicnt2 usicnt1 usicnt0 page 136 0x0d (0x2d) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc page 137 0x0c (0x2c) gpior2 general purpose i/o register 2 page 24 0x0b (0x2b) gpior1 general purpose i/o register 1 page 24 0x0a (0x2a) gpior0 general purpose i/o register 0 page 24 notes: 1. for compatibility with future device s, reserved bits should be written to zero if accessed. reserved i/o memory address es should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operation the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 210 7753f?avr?01/11 attiny261/attiny461/attiny861 0x09 (0x29) acsrb hsel hlev acm2 acm1 acm0 page 143 0x08 (0x28) acsra acd acbg aco aci acie acme acis1 acis0 page 140 0x07 (0x27) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 page 157 0x06 (0x26) adcsra aden adsc adate adif adie adps2 adps1 adps0 page 160 0x05 (0x25) adch adc data register high byte page 161 0x04 (0x24) adcl adc data register low byte page 161 0x03 (0x23) adcsrb bin gsel refs2mux5adts2adts1adts0 page 162 0x02 (0x22) didr1 adc1 0d adc9d adc8d adc7d page 163 0x01 (0x21) didr0 adc6d adc5d adc 4d adc3d arefd adc2d adc1d adc0d page 163 0x00 (0x20) tccr1e ? - oc1oe5 oc1oe4 oc1oe3 oc1oe2 oc1oe1 oc1oe0 page 122 25. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future device s, reserved bits should be written to zero if accessed. reserved i/o memory address es should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operation the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 211 7753f?avr?01/11 attiny261/attiny461/attiny861 26. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o regi ster cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 212 7753f?avr?01/11 attiny261/attiny461/attiny861 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a 26. instruction set summary (continued) mnemonics operands description operation flags #clocks 213 7753f?avr?01/11 attiny261/attiny461/attiny861 27. ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive fo r restriction of hazardous s ubstances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 23.3 on page 189 . table 27-1. available product offering ordering code (2) speed (mhz) (3) power supply (v) package (1) operation range attiny261-15sz 16 2.7 - 5.5 tg automotive (-40 to +125c) attiny261-15mz 16 2.7 - 5.5 pn automotive (-40 to +125c) ATTINY261-15XZ 16 2.7 - 5.5 6g automotive (-40 to +125c) attiny261-15maz 16 2.7 - 5.5 pc automotive (-40 to +125c) attiny461-15sz 16 2.7 - 5.5 tg automotive (-40 to +125c) attiny461-15mz 16 2.7 - 5.5 pn automotive (-40 to +125c) attiny461-15xz 16 2.7 - 5.5 6g automotive (-40 to +125c) attiny461-15maz 16 2.7 - 5.5 pc automotive (-40 to +125c) attiny861-15sz 16 2.7 - 5.5 tg automotive (-40 to +125c) attiny861-15mz 16 2.7 - 5.5 pn automotive (-40 to +125c) attiny861-15xz 16 2.7 - 5.5 6g automotive (-40 to +125c) attiny861-15maz 16 2.7 - 5.5 pc automotive (-40 to +125c) package type pn 32-pad, 5.0x5.0 mm body, lead pitch 0.50 mm, quad flat no lead package (qfn) tg 20-lead, 0.300" wide body lead, plastic gull wing small outline package (soic) 6g 20-lead, 4.4x6.5 mm body, 0.65 mm pitch, lead length: 0.6 mm thin shrink small outline package (tssop) pc 20-lead, 4.0x4.0 mm body, 0.50 mm pitch, quad flat no lead package (qfn) 214 7753f?avr?01/11 attiny261/attiny461/attiny861 28. packaging information 28.1 pn 215 7753f?avr?01/11 attiny261/attiny461/attiny861 28.2 tg 216 7753f?avr?01/11 attiny261/attiny461/attiny861 217 7753f?avr?01/11 attiny261/attiny461/attiny861 28.3 6g 218 7753f?avr?01/11 attiny261/attiny461/attiny861 28.4 pc 219 7753f?avr?01/11 attiny261/attiny461/attiny861 29. errata 29.1 errata attiny261 the revision letter in this section refe rs to the revision of the attiny261 device. 29.1.1 rev a trigger reference levels of the analog comparator. 29.2 errata attiny461 the revision letter in this section refe rs to the revision of the attiny461 device. 29.2.1 rev b trigger reference levels of the analog comparator. 29.3 errata attiny861 the revision letter in this section refe rs to the revision of the attiny861 device. 29.3.1 rev b trigger reference levels of the analog comparator. 29.4 errata description 29.4.1 trigger reference levels of the analog comparator the analog comparator should not used with trigger reference levels of less than 300mv with respect to gnd. problem fix/workaround no workaround. 220 7753f?avr?01/11 attiny261/attiny461/attiny861 30. revision history 30.1 7753f-avr-01/11 ? trigger reference levels of the analog comparator errata added 30.2 7753e-avr-06/10 ? ordering information updated ? dc characteristics table updated 30.3 7753d-avr-11/09 ? ordering information updated ? qfn pinout added ? internal rc oscillator accuracy updated 30.4 7753c-avr-07/09 ? qfn package added ? adc characteristics updated ? temps sensor updated ? typical characteristics updated 30.5 7753b-avr-08/08 ? added 6g product offering to ordering information. 30.6 7753a-avr-11/07 ? first datasheet draft - initial automotive version. started from industrial datasheet doc2588 rev.b - 01/07 221 7753f?avr?01/11 attiny261/attiny461/attiny861 31. table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 pin configurations ..... ................ ................. ................ ................. ............ 2 1.1 disclaimer ..........................................................................................................3 1.2 automotive quality grade .................................................................................3 2 overview ............ ................ ................ ............... .............. .............. ............ 4 2.1 block diagram ...................................................................................................4 2.2 pin descriptions .................................................................................................5 3 resources .............. .............. .............. ............... .............. .............. ............ 7 4 about code examples ........ .............. ............... .............. .............. ............ 8 5 avr cpu core .......... ................ ................ ................. ................ ............... 9 5.1 overview ............................................................................................................9 5.2 alu ? arithmetic logic unit .............................................................................10 5.3 status register ................................................................................................11 5.4 general purpose register file ........................................................................12 5.5 stack pointer ...................................................................................................13 5.6 instruction execution timing ...........................................................................14 5.7 reset and interrupt handling ...........................................................................15 6 avr memories .......... ................ ................ ................. ................ ............. 17 6.1 in-system re-programmable flash program memory ....................................17 6.2 sram data memory ........................................................................................17 6.3 eeprom data memory . ................. ................ ............. ............ ............. ..........18 6.4 i/o memory ......................................................................................................22 6.5 register description ........................................................................................22 7 system clock and clock options ................ ................. .............. .......... 25 7.1 clock systems and their distribution ...............................................................25 7.2 clock sources .................................................................................................27 7.3 default clock source .......................................................................................27 7.4 external clock .................................................................................................27 7.5 high frequency pll clock - pllclk .............................................................28 7.6 calibrated internal rc oscillator .....................................................................29 7.7 128 khz internal oscillator ..............................................................................30 7.8 low-frequency crystal oscillator .....................................................................30 222 7753f?avr?01/11 attiny261/attiny461/attiny861 7.9 crystal oscillator .............................................................................................30 7.10 clock output buffer .........................................................................................32 7.11 system clock prescaler ..................................................................................32 7.12 register description ........................................................................................32 8 power management and sleep mo des ............... .............. ............ ........ 35 8.1 sleep modes ....................................................................................................35 8.2 idle mode .........................................................................................................35 8.3 adc noise reduction mode ............................................................................36 8.4 power-down mode ...........................................................................................36 8.5 standby mode .................................................................................................36 8.6 power reduction register ...............................................................................36 8.7 minimizing power consumption ......................................................................36 8.8 register description ........................................................................................38 9 system control and reset ...... ................ ................. ................ ............. 40 9.1 internal voltage reference ..............................................................................44 9.2 watchdog timer ..............................................................................................44 9.3 timed sequences for changing the configuration of the watchdog timer ....45 9.4 register description ........................................................................................45 10 interrupts ............... .............. .............. ............... .............. .............. .......... 50 10.1 interrupt vectors in attiny261/461/861 ...........................................................50 11 external interrupts .......... ................ ................. .............. .............. .......... 52 11.1 register description ........................................................................................52 12 i/o ports ............... ................ .............. ............... .............. .............. .......... 55 12.1 overview ..........................................................................................................55 12.2 ports as general digital i/o .............................................................................56 12.3 alternate port functions ..................................................................................60 12.4 register description ........................................................................................69 13 timer/counter0 prescaler ..... .............. .............. .............. .............. ........ 70 13.1 register description ........................................................................................71 14 timer/counter0 ............... ................ ................. .............. .............. .......... 73 14.1 features ..........................................................................................................73 14.2 overview ..........................................................................................................73 14.3 timer/counter clock sources .........................................................................74 14.4 counter unit ....................................................................................................74 223 7753f?avr?01/11 attiny261/attiny461/attiny861 14.5 modes of operation .........................................................................................75 14.6 input capture unit ...........................................................................................77 14.7 output compare unit .......................................................................................78 14.8 timer/counter timing diagrams .....................................................................79 14.9 accessing registers in 16-bit mode ................................................................81 14.10 register description ........................................................................................85 15 timer/counter1 prescaler ..... .............. .............. .............. .............. ........ 89 15.1 register description ........................................................................................90 16 timer/counter1 ............... ................ ................. .............. .............. .......... 92 16.1 features ..........................................................................................................92 16.2 overview ..........................................................................................................92 16.3 counter unit ....................................................................................................96 16.4 output compare unit .......................................................................................97 16.5 dead time generator ......................................................................................99 16.6 compare match output unit ..........................................................................100 16.7 modes of operation .......................................................................................102 16.8 timer/counter timing diagrams ...................................................................109 16.9 fault protection unit ......................................................................................111 16.10 accessing 10-bit registers ............................................................................112 16.11 register description ......................................................................................115 17 usi ? universal seri al interface ............ ................. ................ ............. 128 17.1 features ........................................................................................................128 17.2 overview ........................................................................................................128 17.3 functional descriptions .................................................................................129 17.4 alternative usi usage ...................................................................................135 17.5 register descriptions ....................................................................................135 18 ac ? analog comparator ... .............. ............... .............. .............. ........ 140 18.1 register description ......................................................................................140 18.2 analog comparator multiplexed input ...........................................................141 19 adc ? analog to digital co nverter .............. .............. .............. ........... 144 19.1 features ........................................................................................................144 19.2 overview ........................................................................................................144 19.3 operation .......................................................................................................145 19.4 starting a conversion ....................................................................................146 224 7753f?avr?01/11 attiny261/attiny461/attiny861 19.5 prescaling and conversion timing ................................................................147 19.6 changing channel or reference selection ...................................................149 19.7 adc noise canceler .....................................................................................151 19.8 adc conversion result .................................................................................154 19.9 temperature measurement ...........................................................................155 19.10 register description ......................................................................................157 20 debugwire on-chip debug s ystem .............. .............. .............. ........ 164 20.1 features ........................................................................................................164 20.2 overview ........................................................................................................164 20.3 physical interface ..........................................................................................164 20.4 software break points ...................................................................................165 20.5 limitations of debugwire .............................................................................165 20.6 register description ......................................................................................165 21 self-programming the flash .. ............... ................. ................ ............. 166 21.1 performing page erase by spm ....................................................................166 21.2 filling the temporary buffer (page loading) .................................................166 21.3 performing a page write ...............................................................................167 21.4 addressing the flash during self-programming ...........................................167 21.5 register description ......................................................................................169 22 memory programming ........ .............. ............... .............. .............. ........ 171 22.1 program and data memory lock bits ...........................................................171 22.2 fuse bytes .....................................................................................................172 22.3 signature bytes .............................................................................................173 22.4 calibration byte .............................................................................................173 22.5 reading the signature row from software ...................................................174 22.6 page size ......................................................................................................174 22.7 parallel programming parameters, pin mapping, and commands ...............174 22.8 parallel programming ....................................................................................176 22.9 serial downloading ........................................................................................183 23 electrical characteristics ... .............. ............... .............. .............. ........ 187 23.1 absolute maximum ratings* .........................................................................187 23.2 dc characteristics .........................................................................................187 23.3 speed grades ...............................................................................................189 23.4 clock characteristics .....................................................................................189 23.5 system and reset characteristics ................................................................190 225 7753f?avr?01/11 attiny261/attiny461/attiny861 23.6 adc characteristics ......................................................................................191 23.7 parallel programming characteristics ...........................................................194 23.8 serial programming characteristics ..............................................................196 24 typical characteristics ....... .............. ............... .............. .............. ........ 197 24.1 active supply current ....................................................................................197 24.2 idle supply current ........................................................................................198 24.3 supply current of i/o modules ......................................................................199 24.4 power-down supply current ..........................................................................200 24.5 pin pull-up .....................................................................................................201 24.6 pin driver strength ........................................................................................202 24.7 pin threshold and hysteresis ........................................................................204 24.8 bod threshold and analog comparator offset ............................................206 24.9 internal oscillator speed .................... ...........................................................207 25 register summary ............ .............. .............. .............. .............. ........... 209 26 instruction set summary ... .............. ............... .............. .............. ........ 211 27 ordering information .......... .............. ............... .............. .............. ........ 213 28 packaging information .......... ................ ................. ................ ............. 214 28.1 pn .................................................................................................................214 28.2 tg .................................................................................................................215 28.3 6g .................................................................................................................217 28.4 pc .................................................................................................................218 29 errata ........... ................ ................ ................. ................ .............. ........... 219 29.1 errata attiny261 ............................................................................................219 29.2 errata attiny461 ............................................................................................219 29.3 errata attiny861 ............................................................................................219 29.4 errata description ..........................................................................................219 30 revision history ....... ................ ................ ................. ................ ........... 220 30.1 7753d-avr-11/09 .........................................................................................220 30.2 7753c-avr-07/09 .........................................................................................220 30.3 7753b-avr-08/08 .........................................................................................220 30.4 7753a-avr-11/07 .........................................................................................220 31 table of contents ....... ................ ................. ................ .............. ........... 221 7753f?avr?01/11 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en-yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2011 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? , avr ? logo, and others are registered trade- marks or trademarks of atmel corporation or its subsidiari es. other terms and product names may be trademarks of others. |
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